FinFET split gate EEPROM structure and method of its fabrication

• US 20060278915A1
• Filed: 06/09/2005
• Published: 12/14/2006
• Est. Priority Date: 06/09/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsao, Hsun-Chih, Chen, Hung-Wei, Lee, Di-Hong, Chen, Kuang-Hsin
• Granted Patent: US 7,205,601 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin'"'"'s sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

Claims

1. A finFET split gate EEPROM structure, comprising:

an elongated, elevated semiconductor fin having a source and a drain formed therein to define a channel therebetween;

a control gate structure straddling the fin and overlying a first portion of the channel, the control gate structure comprising

a tunnel layer on the fin,

a floating electrode on the tunnel layer,

a first insulative stratum over the floating electrode, and

a first conductive stratum on the first insulative stratum; and

a select gate structure straddling the fin and overlying a second portion of the channel, the select gate structure comprising

a second insulating stratum on the fin, and

a second conductive stratum on the second insulative stratum, the second conductive stratum and the first conductive stratum being contiguous portions of a continuous conductive layer.

2. A structure as in claim 1, wherein:

the control gate structure and the first channel portion constitute a memory transistor; and

the select gate structure and the second channel portion constitute a select transistor.

3. A structure as in claim 1, wherein:

the tunnel layer is a thin, high-quality layer SiO₂, Si₃N₄, HfO₂, or Al₂O₃;

the floating electrode is a layer of conductive polysilicon, a conductive metal-containing material, or a matrix of conductive quantum dots or nanospheres;

the insulative strata are silicon dioxide, oxynitride, nitride-oxide, oxide-nitride-oxide, or a high-K dielectric material; and

the conductive strata are polysilicon or a conductive-metal-containing material.

4. A structure as in claim 1, which further comprises an insulative coating on the floating electrode between the floating electrode and the first insulative stratum.

5. A structure as in claim 4, wherein the insulative coating is silicon dioxide, oxynitride, nitride-oxide, oxide-nitride-oxide, of a high-K dielectric material.

6. A structure as in claim 1, wherein:

the first and second insulative strata are portions of a continuous outer insulative layer that resides on the control gate structure and on those surfaces of the fin not straddled by the control gate structure; and

the first and second conductive strata are electrically continuous portions of a continuous outer conductive layer that resides on the outer insulative layer.

7. A structure as in claim 6, which further comprises an insulative, planar, film-coated semiconductor substrate supporting the fin, the planes of the fin and the substrate being non-parallel, the insulative layer covering portions of the film not covered by the fin.

8. A structure as in claim 6, wherein:

the control gate structure and the first channel portion is capable of functioning as a memory transistor; and

the select gate structure and the second channel portion are capable of functioning as a select transistor.

9. A structure as in claim 6, wherein:

the tunnel layer is a thin, high-quality layer of SiO₂, Si₃N₄, HfO₂, or Al₂O₃;

the floating electrode is a layer of conductive polysilicon, a conductive metal-containing material, or a matrix of conductive quantum dots or nanospheres;

the outer insulative layer is silicon dioxide, oxynitride, nitride-oxide, oxide-nitride-oxide, or a high-K dielectric material; and

the outer conductive layer is polysilicon or a conductive metal-containing material.

10. A structure as in claim 6, which further comprises an insulative coating on the floating electrode between the floating electrode and the first insulative stratum.

11. A structure as in claim 6, wherein the insulative coating is silicon dioxide, oxynitride, nitride-oxide, oxide-nitride-oxide, or a high-K dielectric material.

12. A semiconductor structure, comprising:

a generally planar, thin semiconductor member having opposed major surfaces and a source and a drain formed therein to define therebetween a channel that is generally parallel to the major surfaces;

a control gate structure located on the major surfaces of the member so as to overlie both sides of a first portion of the channel, the control gate structure comprising

a tunnel layer on each major surface,

a floating electrode on each tunnel layer,

a first insulative stratum over each floating electrode, and

a first conductive stratum on each first insulative stratum; and

a select gate structure located on the major surfaces of the member so as to overlie a second portion of the channel, the select gate structure comprising

a second insulating stratum on each major surface, and

a second conductive stratum on each second insulative stratum, wherein the second conductive stratum and the first conductive stratum are contiguous portions of a continuous conductive layer.

13. A structure as in claim 12, which further comprises an insulative coating on each floating electrode between the floating electrode and is associated first insulative stratum.

14. A structure as in claim 12, which further comprises:

an outer insulative layer on each control gate structure and on the major surfaces of the member that are not covered by the select gate structure, each insulating layer including a respective insulative stratum as a portion thereof; and

an outer conductive layer on each insulative stratum, each layer including a respective conductive stratum.

15. A structure as in claim 14, wherein the tunnel layers, the floating electrodes, the outer insulative layers, and the outer conductive layers are portions of respective inverted, substantially “

U”

-shaped layers that straddle the member, the floating electrodes and the conductive strata being respectively electrically continuous.

16. A structure as in claim 15, wherein each second conductive stratum and a respective control gate structure are separated by a portion of the substantially “

U”

-shaped insulative layer.

17. A method of fabricating a split gate FinFET EEPROM on a planar semiconductor substrate, which comprises:

(a) covering the substrate with an insulative film;

(b) forming on the insulative film an elevated, extended semiconductor fin having opposed major surfaces that are not parallel with the plane of the substrate;

(c) forming a substantially “

U”

-shaped tunnel layer on the fin'"'"'s major surfaces and over the top of the fin;

(d) forming a substantially “

U”

-shaped floating electrode on the tunnel layer;

(e) forming a separated source and drain in the fin to define therebetween a channel that is parallel to the fin'"'"'s major surfaces so that the tunnel layer overlies a first portion of the channel

(f) forming an outer insulative layer over the floating electrode, on the sides of the floating electrode and the tunnel layer, and on portions of the major surfaces and top of the fin not covered by the tunnel layer; and

(g) forming a continuous outer conductive layer on the insulative layer over both the first channel portion and over a second channel portion that is nearer to the source than to the drain.

18. A method as in claim 17, which further comprises:

between steps (e) and (f), coating the floating electrode with an electrically insulative material.

19. A product made by the process of claim 18.

20. A method as in claim 17, wherein step (e) is effected by ion implantation.