Cyclic pipeline analog to digital converter with enhanced accuracy

• US 20060279448A1
• Filed: 06/07/2006
• Published: 12/14/2006
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Lu, Woody
• Granted Patent: US 7,259,708 B2
• Time in Patent Office: Days
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0663 using clocked averaging
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence

Abstract

A cyclic pipeline analog to digital converter includes a sample/hold module, a sub-analog/digital converting module, and an alternate digital/analog converting module. The sample/hold module generates a sample signal according to an analog-input signal and a residue signal. The sub-analog/digital converting module generates a first control signal and a second control signal alternately in different time according to the converting result of the sample signal. The alternate digital/analog converting module decides to receive a first reference signal and a second reference signal separately according to the first control signal and the second control signal. The alternate digital/analog converting module generates a first transfer signal according to at least the sample signal among the sample signal, the first reference signal and a first feedback signal, and generates a second transfer signal according to at least the sample signal among the sample signal, the second reference signal and a first feedback signal. The alternate digital/analog converting module generates the first feedback signal and the residue signal according to one of the first transfer signal and the second transfer signal.

Claims

1. A cyclic pipeline analog to digital converter, comprising:

a sample/hold module, which generates a sample signal according to an analog-input signal and a residual signal;

a sub-analog/digital converting module, which generates a first control signal and a second control signal at different time alternately according to a digital converting result of the sample signal; and

an alternate digital/analog converting module, which decides to receive a first reference signal and a second reference signal separately according to the first control signal and the second control signal, generates a first transfer signal according to at least the sample signal among the sample signal, the first reference signal and a first feedback signal, generates a second transfer signal according to at least the sample signal among the sample signal, the second reference signal and the first feedback signal, and generates the first feedback signal and the residual signal according to one of the first transfer signal and the second transfer signal.

2. The cyclic pipeline analog to digital converter according to claim 1, further comprising:

a clock generating module, which generates a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are enabled at different time.

3. The cyclic pipeline analog to digital converter according to claim 2, wherein the sub-analog/digital converting module generates the first control signal according to the first clock signal and the digital converting result and generates the second control signal according to the second clock signal and the digital converting result.

4. The cyclic pipeline analog to digital converter according to claim 1, wherein the alternate digital/analog converting module comprises:

a first converting unit, which decides to receive the first reference signal separately according to the first control signal, and generates the first transfer signal according to at least the sample signal among the sample signal, the first reference signal and the first feedback signal;

a second converting unit, which decides to receive the second reference signal separately according to the second control signal, and generates the second transfer signal according to at least the sample signal among the sample signal, the second reference signal and the first feedback signal; and

an amplifying unit, which generates the first feedback signal and the residual signal according to one of the first transfer signal and the second transfer signal, wherein the first feedback signal is inputted to one of the first converting unit and the second converting unit.

5. The cyclic pipeline analog to digital converter according to claim 4, further comprising:

a clock generating module, which generates a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal are enabled at different time.

6. The cyclic pipeline analog to digital converter according to claim 5, wherein the first converting unit decides to receive the first feedback signal according to the second clock signal, and the second converting unit decides to receive the first feedback signal according to the first clock signal.

7. The cyclic pipeline analog to digital converter according to claim 4, wherein the first converting unit comprises:

a first capacitor, which is electrically connected to the amplifying unit, and receives at least the sample signal among the sample signal, the first reference signal and the first feedback signal for generating the first transfer signal;

a first feedback switch, which controls the first capacitor to receive the first feedback signal; and

a first capacitor switch, decides the first capacitor to receive the first reference signal according to the first control signal.

8. The cyclic pipeline analog to digital converter according to claim 4, wherein the second converting unit comprises:

a second capacitor, which is electrically connected to the amplifying unit, and receives at least the sample signal among the sample signal, the second reference signal and the first feedback signal for generating the second transfer signal;

a second feedback switch, which controls the second capacitor to receive the first feedback signal; and

a second capacitor switch, which decides the second capacitor to receive the first reference signal according to the second control signal.

9. The cyclic pipeline analog to digital converter according to claim 4, wherein the amplifying unit comprises:

an amplifier, which generates the first feedback signal and the residual signal according to one of the first transfer signal and the second transfer signal.

10. The cyclic pipeline analog to digital converter according to claim 4, wherein the amplifying unit comprises:

a grounding switch, which decides to ground the first capacitor and a second capacitor separately according to an input clock signal.

11. The cyclic pipeline analog to digital converter according to claim 4, wherein the alternate digital/analog converting module further comprises:

a third converting unit, which decides to receive a third reference signal according to the first control signal and generates a third transfer signal according to at least the sample signal among the sample signal, the third reference signal and a second feedback signal; and

a fourth converting unit, which decides to receive a fourth reference signal according to the second control signal, and generates a fourth transfer signal according to at least the sample signal among the sample signal, the fourth reference signal and the second feedback signal.

12. The cyclic pipeline analog to digital converter according to claim 11, wherein the amplifying unit generates the second feedback signal according to one of the third transfer signal and the fourth transfer signal, and generates the residual signal according to one of the first feedback signal and the second feedback signal, and the second feedback signal is inputted to one of the third converting unit and the fourth converting unit.

13. The cyclic pipeline analog to digital converter according to claim 12, wherein the amplifying unit comprises:

a differential amplifier, which generates the first feedback signal according to one of the first transfer signal and the second transfer signal, generates the second feedback signal according to one of the third transfer signal and the fourth transfer signal, and generates the residual signal according to one of the first feedback signal and the second feedback signal.