Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
First Claim
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11. A graphics card for connection to the motherboard of a computing system having a CPU bus, said graphics card comprising:
- a silicon chip of a monolithic construction implementing a graphics processing and display subsystem including;
(a) multiple GPU-driven pipeline cores;
(b) a routing center, disposed on said CPU bus, for distributing the graphics data stream, coming from said CPU among said GPU-driven pipeline cores, and then collecting the rendered results (frame buffers) from said pipeline cores, to said compositing unit;
(c) a compositing unit for re-composing the partial frame buffers according to said ongoing parallelization mode;
(d) a control unit, for controlling the configuring and functioning of said graphics processing and display system according to the parallelization mode selected at any instant in time;
(d) a processing element (PE) with internal or external memory;
(e) a profiling functions unit, for delivering a benchmarking data to said multi-pipe drivers; and
(f) a display interface, for running single or multiple display screens.
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Abstract
A high performance graphics processing and display system architecture supporting a cluster of multiple cores of graphic processing units (GPUs) that cooperate to provide a powerful and highly scalable visualization solution supporting photo-realistic graphics capabilities for diverse applications. The present invention eliminates rendering bottlenecks along the graphics pipeline by dynamically managing various parallel rendering techniques and enabling adaptive handling of diverse graphics applications.
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Citations
33 Claims
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11. A graphics card for connection to the motherboard of a computing system having a CPU bus, said graphics card comprising:
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a silicon chip of a monolithic construction implementing a graphics processing and display subsystem including;
(a) multiple GPU-driven pipeline cores;
(b) a routing center, disposed on said CPU bus, for distributing the graphics data stream, coming from said CPU among said GPU-driven pipeline cores, and then collecting the rendered results (frame buffers) from said pipeline cores, to said compositing unit;
(c) a compositing unit for re-composing the partial frame buffers according to said ongoing parallelization mode;
(d) a control unit, for controlling the configuring and functioning of said graphics processing and display system according to the parallelization mode selected at any instant in time;
(d) a processing element (PE) with internal or external memory;
(e) a profiling functions unit, for delivering a benchmarking data to said multi-pipe drivers; and
(f) a display interface, for running single or multiple display screens. - View Dependent Claims (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15, 16, 17, 18, 19, 20, 21)
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12-1. The graphics card of claim 11, wherein said silicon chip has multiple GPU-driven pipeline cores each with graphic processing unit (GPU) that supports the parallelization of image processing using one or more parallelization modes, and being adapted for interfacing with a computing system having a means for displaying images on at least one computer screen and supporting (i) one or more software applications for issuing graphics commands, (ii) one or more graphic libraries (state machines) for storing data used to implement said graphics commands, and (iii) multi-pipe drivers for allowing said GPU-drive pipeline cores to interact with said graphic libraries.
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22. A computer system for display images on more or more display screens, comprising:
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a motherboard having a CPU bus and a silicon chip of a monolithic construction for implementing a graphics processing and display subsystem, said silicon chip including;
(a) multiple GPU-driven pipeline cores;
(b) a routing center, disposed on said CPU bus, for distributing the graphics data stream, coming from said CPU among said GPU-driven pipeline cores, and then collecting the rendered results (frame buffers) from said pipeline cores, to said compositing unit, wherein the way said data is distributed is dictated by said control unit, and depending on the current parallelization mode;
a compositing unit for re-composing the partial frame buffers according to said ongoing parallelization mode;
a control unit, for controlling the configuring and functioning of said graphics processing and display system according to the parallelization mode selected at any instant in time;
a processing element (PE) with internal or external memory;
a profiling functions unit, for delivering a benchmarking data to said multi-pipe drivers; and
a display interface, for running single or multiple display screens. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33-57. -57. (canceled)
Specification