Fringe field switching mode LCD
First Claim
1. A fringe field switching mode LCD comprising:
- a lower substrate having a gate bus line and a data bus line arranged to cross each other and form unit pixels and a counter electrode and a pixel electrode positioned within each unit pixel region with a gate insulator interposed between them and an upper substrate provided with a color filter corresponding to each pixel region and bonded to the lower substrate with a liquid crystal layer interposed between them, wherein the pixel electrode comprises;
first pixel electrodes positioned on the gate insulator while being spaced from each other and second pixel electrodes positioned between the respective first pixel electrodes with a predetermined angle relative to them.
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Abstract
A fringe field switching mode LCD includes a lower substrate having a gate bus line and a data bus line arranged to cross each other and form unit pixels and a counter electrode and a pixel electrode positioned within each unit pixel region with a gate insulator interposed between them and an upper substrate provided with a color filter corresponding to each pixel region and bonded to the lower substrate with a liquid crystal layer interposed between them. The pixel electrode includes first pixel electrodes positioned on the gate insulator while being spaced from each other and second pixel electrodes positioned between the respective first pixel electrodes with a predetermined angle relative to them.
7 Citations
5 Claims
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1. A fringe field switching mode LCD comprising:
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a lower substrate having a gate bus line and a data bus line arranged to cross each other and form unit pixels and a counter electrode and a pixel electrode positioned within each unit pixel region with a gate insulator interposed between them and an upper substrate provided with a color filter corresponding to each pixel region and bonded to the lower substrate with a liquid crystal layer interposed between them, wherein the pixel electrode comprises;
first pixel electrodes positioned on the gate insulator while being spaced from each other and second pixel electrodes positioned between the respective first pixel electrodes with a predetermined angle relative to them. - View Dependent Claims (2, 3, 4, 5)
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Specification