Ferroelectric memory device having ferroelectric capacitor
First Claim
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1. A ferroelectric memory device comprising:
- a cell block including a ferroelectric capacitor and a transistor switch, the ferroelectric capacitor storing binary data by a direction of polarization of the ferroelectric capacitor;
a bit line which is connected to the cell block and applies a voltage to one electrode of the ferroelectric capacitor;
a plate line which is connected to the cell block and applies a voltage to the other electrode of the ferroelectric capacitor;
a word line connected to a gate electrode of the transistor switch; and
a differential amplifier connected to the bit line, in a read operation of the data, a first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a change in voltage of the bit line when the transistor switch is activated being detected by the differential amplifier to read the data, and in a write operation of the data, a second voltage different from the first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a voltage which is higher than the second voltage or lower than the second voltage being applied to the bit line to write data in the ferroelectric capacitor.
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Abstract
A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of the ferroelectric capacitor. In a read operation of data, a first voltage is applied to the plate line. In a write operation of data, a second voltage different from the first voltage is applied to the plate line, and a voltage which is higher or lower than the second voltage is applied to the bit line.
37 Citations
16 Claims
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1. A ferroelectric memory device comprising:
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a cell block including a ferroelectric capacitor and a transistor switch, the ferroelectric capacitor storing binary data by a direction of polarization of the ferroelectric capacitor;
a bit line which is connected to the cell block and applies a voltage to one electrode of the ferroelectric capacitor;
a plate line which is connected to the cell block and applies a voltage to the other electrode of the ferroelectric capacitor;
a word line connected to a gate electrode of the transistor switch; and
a differential amplifier connected to the bit line, in a read operation of the data, a first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a change in voltage of the bit line when the transistor switch is activated being detected by the differential amplifier to read the data, and in a write operation of the data, a second voltage different from the first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a voltage which is higher than the second voltage or lower than the second voltage being applied to the bit line to write data in the ferroelectric capacitor. - View Dependent Claims (2, 15, 16)
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3. A ferroelectric memory device comprising:
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unit cells each including a ferroelectric capacitor and a transistor switch, the unit cell storing binary data by a direction of polarization of the ferroelectric capacitor;
a cell block including the unit cell, the cell block including a 1T1C-type structure holding 1-bit data by the unit cell;
a bit line which is connected to the cell block and applies a voltage to one electrode of the ferroelectric capacitor;
a plate line which is connected to the cell block and applies a voltage to the other electrode of the ferroelectric capacitor;
a word line connected to a gate electrode of the transistor switch; and
a differential amplifier connected to the bit line, wherein in a read operation of the data, a first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a change in voltage of the bit line when the transistor switch is activated being detected by the differential amplifier to read the data, and in a write operation of the data, a second voltage different from the first voltage being applied to the plate line, a predetermined voltage being applied to the word line to activate the transistor switch for a predetermined period of time, and a voltage which is higher than the second voltage or lower than the second voltage being applied to the bit line to write data in the ferroelectric capacitor. - View Dependent Claims (4, 5, 6, 7)
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8. A ferroelectric memory device comprising:
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first unit cells each including a first ferroelectric capacitor and a first transistor switch, the first unit cell storing binary data by a direction of polarization of the first ferroelectric capacitor;
second unit cells each including a second ferroelectric capacitor and a second transistor switch, the second unit cell storing binary data by a direction of polarization of the second ferroelectric capacitor;
a cell block having the first unit cell and the second unit cell, the cell block having a 2T2C-type structure holding 1-bit data by the first unit cell and the second unit cell;
a first bit line which is connected to the cell block and applies a voltage to one electrode of the first ferroelectric capacitor;
a second bit line which is connected to the cell block and applies a voltage to one electrode of the second ferroelectric capacitor;
a first plate line which is connected to the cell block and applies a voltage to the other electrode of the first ferroelectric capacitor;
a second plate line which is connected to the cell block and applies a voltage to the other electrode of the second ferroelectric capacitor;
a word line connected to gate electrodes of the first transistor switch and the second transistor switch; and
a differential amplifier connected to the first bit line and the second bit line, wherein in a reading operation of the data, a first voltage being applied to the first plate line and the second plate line, a predetermined voltage being applied to the word line to activate the first transistor switch and the second transistor switch for a predetermined period of time, and changes in voltage of the first bit line and the second bit line when the first transistor switch and the second transistor switch are activated being detected by the differential amplifier to read data, and in a write operation of the data, a second voltage different from the first voltage being applied to the first plate line and the second plate line, a predetermined voltage being applied to the word line to activate the first transistor switch and the second transistor switch for a predetermined period of time, and a voltage which is higher than the second voltage or lower than the second voltage being applied to the first bit line and the second bit line to write data in the first ferroelectric capacitor and the second ferroelectric capacitor. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification