NAND TYPE FLASH MEMORY ARRAY AND METHOD FOR OPERATING THE SAME

• US 20060279991A1
• Filed: 06/12/2006
• Published: 12/14/2006
• Est. Priority Date: 06/11/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Seoul National University Industry Foundation (Seoul National University)
• Original Assignee: Samsung Electronics Co. Ltd., Seoul National University Industry Foundation (Seoul National University)
• Inventors: PARK, Il Han, KIM, Tae-Hoon, PARK, Byung-Gook
• Granted Patent: US 7,502,262 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND type flash memory array which is composed of a plurality of memory cells with a shallow junction on an SOI substrate to make the body region depleted fully when each channel of the memory cells is turned on is provided. The invention improves the efficiency of a reading operation, enables an erasing operation on the SOI structure and enables use of a low voltage V_PASS instead of a high voltage V_PASS, which is used for a programming operation in a conventional NAND type flash memory array, and therefore it diminishes programming disturbance more effectively than a conventional array.

Claims

1. A NAND type flash memory array comprising:

one or more bit lines on an SOI substrate;

a first selective gate line arranged vertically to the bit lines;

a plurality of word lines arranged vertically to the bit lines;

a second selective gate line arranged vertically to the bit lines;

a common source line arranged vertically to the bit lines; and

a plurality of memory cells connected in series with a first selective transistor and a second selective transistor along each bit line,

wherein the NAND type flash memory array includes a body biasing contact region which is connected to an active region on the lower part of one side of the second selective gate line.

2. The array of claim 1, wherein the SOI substrate is P-type, N-type impurities are injected into the common source line with deep junction, and P-type impurities are injected into the body biasing contact region with deep junction.

3. The array of claim 2, wherein N-type impurities are injected into the source/drain region(common source/drain region) of the memory cells, which are connected to the each bit line in series, the depth of the junction is so shallow that a conduction path can be formed on the lower part of the common source/drain region.

4. The array of claim 1, wherein the silicon layer of the SOI substrate is shallow in order to make the body region of the memory cells depleted fully when the memory cells are turned on.

5. The array of claim 2, wherein the silicon layer of the SOI substrate is shallow in order to make the body region of the memory cells depleted fully when the memory cells are turned on.

6. The array of claim 3, wherein the silicon layer of the SOI substrate is shallow in order to make the body region of the memory cells depleted fully when the memory cells are turned on.

7. The array of claim 4, wherein the memory cells are charge trap memory cells.

8. The array of claim 5, wherein the memory cells are charge trap memory cells.

9. The array of claim 6, wherein the memory cells are charge trap memory cells.

10. A method for operating a NAND type flash memory array, wherein the array comprises one or more bit lines on an SOI substrate, a first selective gate line arranged vertically to the bit lines, a plurality of word lines arranged vertically to the bit lines, a second selective gate line arranged vertically to the bit lines, a common source line arranged vertically to the bit lines, a plurality of memory cells connected in series with a first selective transistor and a second selective transistor along each bit line, and a body biasing contact region which is connected to an active region on the lower part of one side of the second selective gate line, the method comprising:

programming the array by applying a predetermined bias voltage to the each bit line, a plurality of word lines, the first selective gate line, the second selective gate line, the common source line and the body biasing contact region, respectively, to select a specific cell from a plurality of memory cells and inject electrons in the channel to the selected memory cell by F-N tunneling; and

erasing the array by changing the bias voltage condition to inject holes in the body region by F-N tunneling.

11. The method of claim 10, wherein the programming operation includes:

applying a specific voltage V_SG1 to the first selective gate line;

applying a lower voltage V_SEL than the voltage V_SG1 to the bit line, where the source/drain of the selected memory cell is connected electrically to the other cells in series, in order to turn on the first selective transistor;

applying the same or a higher voltage V_UNS than the voltage V_SG1 to the other bit lines in order to turn off the first selective transistor;

applying a higher voltage V_PGM than the voltage V_SEL to the word line, to which the gate of the selected memory cell is connected electrically, in order to generate F-N tunneling by channel electrons;

applying a higher voltage V_PASS than the voltage V_SEL but lower than the voltage V_PGM to the other word lines to turn on each channel of the other cells and not to generate F-N tunneling by the channel electrons;

applying the same voltage V_SG2 as the voltage V_SEL to the second selective gate line to turn off the second selective transistor; and

applying the same voltage Vs as the voltage V_SEL to the common source line.

12. The method of claim 11, wherein, for programming operation, the voltage V_SG1 and the voltage V_UNS are V_CC, the voltage V_SEL, V_SG2 and V_S are 0V (ground), the voltage V_PGM is between 15V and 20V, and the voltage V_PASS is between 4V and 5V.

13. The method of claim 10, wherein the erasing operation includes:

floating the first selective gate line, the second selective gate line and the common source line;

applying a specific voltage V_ERS to all word lines of the block including the specific memory cell; and

applying a higher voltage V_B than the voltage V_ERS to the body biasing contact region in order to generate F-N tunneling by the holes in the body of memory cells.

14. The method of claim 13, wherein the voltage V_ERS is 0V (ground) and the voltage V_B is between 15V and 21V.