PLL circuit and semiconductor device provided with PLL circuit

• US 20060280277A1
• Filed: 06/12/2006
• Published: 12/14/2006
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hachigo, Taketo, Tashiro, Tomonari
• Granted Patent: US 7,616,071 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop

Abstract

Disclosed is a PLL circuit of a small circuit size capable of generating clock including a jitter component with ease. A phase comparator 11 compares the phase of an input reference clock signal CKR to the phase of a signal fed back from a frequency divider 14 to route an output signal corresponding to the phase difference to a filter unit 12. The filter unit 12 detects a low frequency component of the output signal of the phase comparator 11 to route the so detected component to a voltage controlled oscillator 13. The voltage controlled oscillator 13 generates, as an output signal CKF, an oscillation signal of an oscillation frequency which is controlled on the basis of the output voltage of the filter unit 12. The frequency divider 14 divides the frequency of the output signal CKF to output the resulting signal to the phase comparator 11. An end A of a wiring of a wiring part 15 is connected to an output P of the filter unit 12 in such a manner that noise will be induced from outside and added to the output signal of the filter unit 12. The oscillation frequency of the output signal CKF, generated by the voltage controlled oscillator 13, is subjected to variations by noise.

Claims

1. A PLL circuit comprising:

a phase comparator that compares the phase of a reference input signal to that of a feedback output signal of a frequency divider to output a signal corresponding to the phase difference therebetween;

a filter unit that passes a low frequency component of an output signal of said phase comparator;

a voltage controlled oscillator that generates an oscillation signal of an oscillation frequency controlled based on an output voltage from said filter unit; and

said frequency divider that frequency-divides said oscillation signal to output the resulting signal to said phase comparator;

said PLL circuit further comprising;

a wiring part that induces noise from outside;

the noise signal, induced in said wiring part, being added to an output signal from said filter unit.

2. The PLL circuit according to claim 1 wherein an end of a wiring, included in said wiring part, is connected to an input end of said voltage controlled oscillator.

3. The PLL circuit according to claim 1 wherein said wiring part includes a wiring arranged in proximity to at least one of a power supply line and a grounding line.

4. The PLL circuit according to claim 3 wherein said wiring part includes one or more switch units for making adjustable the effective length of said wiring.

5. The PLL circuit according to claim 4 wherein said switch unit includes first and second switch devices, connected in cascade with each other at a connection point of wiring segments of said wiring, and a third switch device, connected across a junction of said first and second switch devices and a ground or a power supply, said third switch device performing an opening/closing operation in reverse to said first and second switch devices.

6. The PLL circuit according to claim 5 wherein said first to third switch devices are MOS transistors controlled in opening/closing by control signals applied to the gates thereof.

7. A semiconductor device provided with the PLL circuit according to claim 1.

8. A PLL circuit comprising:

a phase comparator that compares the phase of a reference input signal to that of a feedback output signal of a frequency divider to output a signal corresponding to the phase difference therebetween;

a filter unit that passes a low frequency component of an output signal of said phase comparator;

a voltage controlled oscillator that generates an oscillation signal of an oscillation frequency controlled on the basis of an output voltage of said filter unit,

and said frequency divider that frequency-divides said oscillation signal to output the resulting signal to said phase comparator;

said PLL circuit further comprising;

a wiring part that induces noise from outside; and

a low-pass filter LPF connected to said wiring part;

the noise signal, induced in said wiring part, being added via said LPF to an output signal from said filter unit.

9. The PLL circuit according to claim 8 wherein the cut-off frequency of said LPF is made controllable.

10. The PLL circuit according to claim 9 wherein said LPF includes a switch that intermittes an output signal of said LPF.

11. The PLL circuit according to claim 10 wherein there are provided a plurality of sets each being composed of said wiring part and said LPF.

12. The PLL circuit according-to claim 10 wherein said wiring part includes a wiring located in proximity to a noise source.

13. The PLL circuit according to claim 12 wherein said wiring part includes one or more switch units that make adjustable the effective length of said wiring.

14. The PLL circuit according to claim 13 wherein said switch unit includes first and second switch devices, connected in cascade with each other at a connection point of wiring segments of said wiring, and a third switch device, connected across a junction of said first and second switch devices and a ground or a power supply, said third switch device performing an opening/closing operation in reverse to said first and second switch devices.

15. The PLL circuit according to claim 14 wherein said first to third switch devices are MOS transistors controlled in opening/closing by control signals applied to the gates thereof.

16. A semiconductor device including the PLL circuit as defined in claim 8.