POLISHING PAD AND METHOD OF PRODUCING THE SAME

• US 20060280930A1
• Filed: 08/24/2006
• Published: 12/14/2006
• Est. Priority Date: 11/13/2001
• Status: Active Grant

• Current Assignee: ROHM and HAAS Electronic Materials CMP Holdings Incorporated (DuPont de Nemours, Inc.)
• Original Assignee: Atsushi Kazuno, Hiroshi Seyanagi, Kazuyuki Ogawa, Koichi Ono, Masahiko Nakamori, Shigeru Komai, Takashi Masui, Takatoshi Yamada, Tetsuo Shimomura, Tsuyoshi Kimura
• Inventors: KAZUNO, Atsushi, ONO, Koichi, Masui, Takashi, KOMAI, Shigeru, OGAWA, Kazuyuki, YAMADA, Takatoshi, NAKAMORI, Masahiko, SHIMOMURA, Tetsuo, KIMURA, Tsuyoshi, Seyanagi, Hiroshi
• Granted Patent: US 7,488,236 B2
• Time in Patent Office: Days
• US Class Current: 428/304.400
• CPC Class Codes: B24B 37/24 characterised by the composition or properties of the pad materials
• CPC Class Codes: B24D 18/00 Manufacture of grinding tools or other grinding devices, e.g. wheels, not otherwise provided for
• CPC Class Codes: B24D 3/30 for close-grained structure
• CPC Class Codes: C08G 18/00 Polymeric products of isocyanates or isothiocyanates
• CPC Class Codes: C08G 18/10 Prepolymer processes involving reaction of isocyanates or isothiocyanates with compounds having active hydrogen in a first reaction step
• CPC Class Codes: C08G 18/12 using two or more compounds having active hydrogen in the first polymerisation step
• CPC Class Codes: C08G 18/3243 containing two or more aromatic rings
• CPC Class Codes: C08G 18/3814 Polyamines
• CPC Class Codes: C08G 18/4211 derived from aromatic dicarboxylic acids and dialcohols
• CPC Class Codes: C08G 18/4236 containing only aliphatic groups
• CPC Class Codes: C08G 18/4808 Mixtures of two or more polyetherdiols
• CPC Class Codes: C08G 18/4854 Polyethers containing oxyalkylene groups having four carbon atoms in the alkylene group
• CPC Class Codes: C08G 18/5096 containing silicon
• CPC Class Codes: C08G 18/61 Polysiloxanes
• CPC Class Codes: C08G 18/664 with compounds of group C08G18/3203
• CPC Class Codes: C08G 18/6674 with compounds of group C08G18/3203
• CPC Class Codes: C08G 18/724 Combination of aromatic polyisocyanates with (cyclo)aliphatic polyisocyanates
• CPC Class Codes: C08G 2101/00 Manufacture of cellular products
• CPC Class Codes: C08G 2110/0066 ≥ 150kg/m3
• CPC Class Codes: C08J 2205/052 Closed cells, i.e. more than 50% of the pores are closed
• CPC Class Codes: C08J 2375/04 : Polyurethanes
• CPC Class Codes: C08J 2483/00 : Characterised by the use of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen, or carbon only; Derivatives of such polymers
• CPC Class Codes: C08J 9/0061 : characterized by the use of several polymeric components
• CPC Class Codes: C08L 83/00 : Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers
• CPC Class Codes: C09D 175/08 : from polyethers
• CPC Class Codes: H01L 21/30625 : With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: Y10T 428/249953 : Composite having voids in a component [e.g., porous, cellular, etc.]
• CPC Class Codes: Y10T 428/249976 : Voids specified as closed

Abstract

The invention provides a polishing pad by which optical materials such as lenses, reflecting mirrors etc., or materials requiring a high degree of surface planarity, as in the polishing of silicone wafers, glass substrates or aluminum substrates for hard disks, or general metal polishing, can be flattened with stability and high polishing efficiency. The invention also provides a polishing pad for semiconductor wafers, which is superior in planarizing characteristic, is free from scratches and can be produced at low cost. There is provided a polishing pad which is free from dechucking error so that neither damage to wafers nor decrease in operating efficiency occurs. There is provided a polishing pad which is satisfactory in planarity, within wafer uniformity, and polishing rate and produces less change in polishing rate. There is provided a polishing pad which can make planarity improvement and scratch decrease compatible.

Claims

1-15. -15. (canceled)

16. A method of polishing a semiconductor wafer, which comprises:

providing a semiconductor wafer polishing pad having a polishing layer constituted by resin foam of closed-cell type, wherein the number of closed cells in the polishing layer is 200 to 600 per mm²; and

rotating the polishing pad and simultaneously positioning the polishing pad to abut on a semiconductor wafer while supplying an abrasive between the polishing layer and the semiconductor wafer.

17. The method of polishing a semiconductor wafer according to claim 16, wherein the polishing layer is polyurethane resin foam containing 0.05 to 5 wt % silicone-based surfactant.

39. The method according to claim 16, wherein the average diameter of the closed cells in the polishing layer is 30 to 60 μ

m.

18-38. -38. (canceled)

40. A method of polishing a semiconductor wafer, which comprises:

providing a semiconductor wafer polishing pad having a polishing layer constituted by resin foam of closed-cell type, wherein the number of closed cells in the polishing layer is 200 to 600 per mm², and the average diameter of the closed cells is 30 to 60 μ

m; and

rotating the polishing pad and simultaneously positioning the polishing pad to abut on a semiconductor wafer while supplying an abrasive between the polishing layer and the semiconductor wafer.

41. The method according to claim 40, wherein the polishing layer is polyurethane resin foam containing 0.05 to 5 wt % silicone-based surfactant.

48. The method according to claim 40, wherein the storage elastic modulus of the resin foam or the resin layer at 40°

C. is 270 MPa or more.

49. The method according to claim 40, wherein the resin foam or the resin layer is polyurethane resin foam.

50. The method according to claim 49, wherein the density of the polyurethane resin foam is 0.67 to 0.90 g/cm³.

51. The method according to claim 49, wherein the polyurethane resin foam contains 0.05 to 5 wt % silicone-based surfactant.

52. The method according to claim 51, wherein the silicone-based surfactant is a polyalkylsiloxane/polyether copolymer.

53. The method according to claim 40, wherein the hardness of the polishing layer is from 45 or more to less than 65 as determined by a D-type rubber hardness meter.

54. The method according to claim 40, wherein the compressibility of the polishing layer is 0.5 to 5%.

55. The method according to claim 40, which is composed of at least 2 layers comprising a polishing layer and a cushion layer softer than the polishing layer laminated therein.

56. The method according to claim 55, wherein the cushion layer is selected from a nonwoven polyester fabric impregnated with urethane, polyurethane foam, and polyethylene foam.

42. A method of polishing a semiconductor wafer, which comprises:

providing a polishing pad having a polishing layer comprising resin foam, wherein the thermal change in dimension of the polishing layer is 3% or less; and

rotating the polishing pad and simultaneously positioning the polishing pad to abut on a semiconductor wafer while supplying an abrasive between the polishing layer and the semiconductor wafer.

43. The method according to claim 42, wherein the polishing layer is polyurethane resin foam containing 0.05 to 5 wt % silicone-based surfactant.

44. A method of polishing a semiconductor wafer, which comprises:

providing a polishing pad having a polishing layer comprising resin foam, wherein the dynamic coefficient of friction of the surface of the polishing layer is 0.1 to 1.0; and

rotating the polishing pad and simultaneously positioning the polishing pad to abut on a semiconductor wafer while supplying an abrasive between the polishing layer and the semiconductor wafer.

45. The method according to claim 44, wherein the polishing layer is polyurethane resin foam containing 0.05 to 5 wt % silicone-based surfactant.

46. A method of polishing a semiconductor wafer, which comprises:

providing a polishing pad having a polishing layer consisting of a resin layer, wherein the difference in the abrasion loss of the polishing layer in a Taber abrasion test before and after a test of dipping it in an aqueous solution (40°

C.) of potassium hydroxide, pH 12.5, for 24 hours is 10 mg or less; and

rotating the polishing pad and simultaneously positioning the polishing pad to abut on a semiconductor wafer while supplying an abrasive between the polishing layer and the semiconductor wafer.

47. The method according to claim 46, wherein the polishing layer is polyurethane resin foam containing 0.05 to 5 wt % silicone-based surfactant.