6F2 access transistor arrangement and semiconductor memory device

• US 20060281250A1
• Filed: 12/15/2004
• Published: 12/14/2006
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schloesser, Till
• Granted Patent: US 7,476,920 B2
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An access transistor arrangement is provided for a 6F² stacked capacitor DRAM memory cell layout with shared bit line contacts. The access transistors are arranged in pairs along semiconductor lines. The two transistors of each pair of transistors are arranged laterally reversed opposing the respective common bit line section. Each pair of access transistors is separated from the adjacent pair of access transistors by an isolation transistor which is permanently turned off. The access transistors and the isolation transistors are formed as identical recessed channel transistors with elongated channel and enhanced isolation properties. The same dopant concentration may be provided for both junctions of the access transistors. As identical devices are provided both as access transistor and as isolation transistors, the complexity of lithographic patterning processes is reduced.

Claims

1. An access transistor arrangement, comprising:

a semiconductor substrate;

a first access transistor and a second access transistor, each access transistor having a gate electrode and an active area, the active area being formed within the semiconductor substrate;

each active area comprising a bit line contact section, a node contact section and a channel section, the bit line contact section and the node contact section being adjacent to a pattern surface of the substrate, and the channel section separating the bit line contact section and the node contact section; and

each gate electrode being disposed in part over the pattern surface and in part in recess grooves, the recess grooves being formed in the substrate between the respective node contact section and the respective bit line contact section, and each gate electrode being separated from the respective channel section by a gate dielectric, the access transistor arrangement further comprising;

an isolation transistor being arranged between the first and the second access transistor, the first and the second access transistor facing laterally reversed opposed the isolation transistor, the node contact section of the first access transistor and the node contact section of the second access transistor being adjacent to the isolation transistor;

the isolation transistor being controlled by an isolation gate line, the isolation gate line being disposed in part over the pattern surface and in part in an isolation groove and being separated from the substrate by an isolation gate dielectric, the isolation groove being formed in the substrate between the node contact sections of the first and the second access transistor.

2. The access transistor arrangement of claim 1, wherein the recess grooves of the access transistors and the isolation groove have the same shape.

3. The access transistor arrangement of claim 2, wherein the recess grooves of the access transistors and the isolation groove have the same size.

4. The access transistor arrangement of claim 3, wherein the recess grooves of the access transistors and the isolation groove result from a common patterning process.

5. The access transistor arrangement of claim 4, wherein the recess grooves and the isolation groove are U-shaped.

6. The access transistor arrangement of claim 1, wherein a turn-off voltage applied to the isolation gate is equal to a voltage applied to the gate electrodes to turn off the access transistors.

7. The access transistor arrangement of claim 1, wherein the node contact sections and the bit line contact sections are formed as doped regions of a first conductivity type;

the channel regions are formed as intrinsic regions or as doped regions of a second conductivity type, wherein the second conductivity type is the opposite of the first conductivity type, and wherein

the node contact sections and the bit line contact sections have the same dopant concentration.

8. The access transistor arrangement of claim 1, further comprising a third access transistor, a forth access transistor and a further isolation transistor;

wherein the third access transistor, the forth access transistor and the further isolation transistor are arranged relative to each other corresponding to the first access transistor, the second access transistor and the isolation transistor;

wherein the third access transistor is arranged adjacent to the second access transistor such that the bit line contact section of the second access transistor and the bit line contact section of the third access transistor form a common bit line contact section and such that the active areas of the second and the third access transistors form a contiguous semiconductor line.

9. The access transistor arrangement of claim 7, further comprising further semiconductor lines, the semiconductor lines being separated by row insulating lines, wherein the gate electrodes are sections of word lines, and wherein the word lines extend perpendicularly to the semiconductor lines.

10. A semiconductor memory device, comprising:

a semiconductor substrate;

a first access transistor and a second access transistor, each access transistor having a gate electrode and an active area, the active area being formed within the semiconductor substrate;

each active area comprising a bit line contact section, a node contact section and a channel section, the bit line contact section and the node contact section being adjacent to a pattern surface of the substrate, and the channel section separating the bit line contact section and the node contact section; and

each gate electrode being disposed at least in parts in recess grooves, the recess grooves being formed in the substrate between the respective node contact section and the respective bit line contact section and each gate electrode being separated from the respective channel section by a gate dielectric;

the semiconductor memory device further comprising;

storage capacitors being disposed above the pattern surface, each storage capacitor being coupled to one of the node contact sections;

a bit line, the bit line being coupled to the bit line contact sections; and

an isolation transistor being arranged between the first and the second access transistor, the first and the second access transistor facing laterally reversed opposing the isolation transistor, the node contact section of the first access transistor and the node contact section of the second access transistor being adjacent to the isolation transistor;

the isolation transistor being controlled by an isolation gate line, the isolation gate line being disposed at least in part in an isolation groove formed in the substrate between the node contact sections of the first and the second access transistor and being separated from the substrate by an isolation gate dielectric.

11. The semiconductor memory device of claim 10, wherein the recess grooves of the access transistors and the isolation groove have the same shape.

12. The semiconductor memory device of claim 11, wherein the recess grooves of the access transistors and the isolation groove have the same size.

13. The semiconductor memory device of claim 12, wherein the recess grooves of the access transistors and the isolation groove result from a common patterning process.

14. The semiconductor memory device of claim 10, wherein the recess grooves and the isolation groove are U-shaped.

15. The semiconductor memory device of claim 10, wherein a turn-off voltage applied to the isolation gate is equal to a voltage being applied to the gate electrodes to turn off the access transistors.

16. A semiconductor memory device, comprising:

a semiconductor substrate;

a plurality of first access transistors and a plurality of second access transistors, each access transistor having a gate electrode and an active area, the active area being formed within the semiconductor substrate;

each active area comprising a bit line contact section, a node contact section and a channel section, the bit line contact section and the node contact section being adjacent to a pattern surface of the substrate and the channel section separating the bit line contact section and the node contact section; and

each gate electrode being disposed in part above the pattern surface and in part in recess grooves, the recess grooves being formed in the substrate between the respective node contact section and the respective bit line contact section, and each gate electrode being separated from the respective channel section by a gate dielectric;

the semiconductor memory device further comprising;

a plurality of isolation transistors, each isolation transistor being arranged between a pair of one of the first and one of the second access transistors, the first and the second access transistor facing laterally reversed opposing the isolation transistor, the node contact section of the first access transistor and the node contact section of the second access transistor being adjacent to the isolation transistor;

a plurality of isolation gate lines being separated from the substrate by an isolation gate dielectric and being disposed at least in parts in isolation grooves, the isolation grooves being formed in the substrate between the node contact sections of the first and the second access transistor;

wherein a plurality of the access transistors are arranged in lines such that the bit line contact sections of neighboring first and second access transistors form a common bit line contact section and such that the active areas of the access transistors form a contiguous semiconductor line.