Method for forming a sealed storage non-volative multiple-bit memory cell

• US 20060281255A1
• Filed: 06/14/2005
• Published: 12/14/2006
• Est. Priority Date: 06/14/2005
• Status: Abandoned Application

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chiu, Chun-Jen, Liu, Kuang-Wen, Chen, Hsin-Huei, Huang, Jen-Ren
• Application Number:
  US11/153,690
• Publication Number:
  US 20060281255A1
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of fabricating an array of trapped charge memory cells is described that eliminates bird'"'"'s beak issues. Implants at a tilt angle form pockets in a substrate that reduce problems resulting from a short channel effect.

Claims

1. A method for forming an array of trapped charge memory cells, comprising:

providing a semiconductor substrate having an oxide-nitride-oxide (ONO) layer formed on a surface thereof;

depositing a first layer of polysilicon over the ONO layer;

removing a portion of the first layer of polysilicon in a reference direction to form at least one gate structure, thereby exposing a portion of the ONO layer;

depositing an oxide spacer on sides of the at least one gate structure and on a portion of the ONO layer;

removing a portion of the ONO layer not covered by the oxide spacer to expose a portion of the substrate; and

forming at least one bit line in the exposed portion of the substrate.

2. The method as set forth in claim 1, wherein the removing of a portion of the first layer of polysilicon is followed by implanting with a tilt angle an implant pocket into the substrate through the ONO layer.

3. The method as set forth in claim 2, wherein the implanting comprises implanting with a tilt angle a plurality of implant pockets through the ONO layer into the substrate and at least partially beneath the at least one gate structure.

4. The method as set forth in claim 2, wherein the forming of at least one bit line comprises placing an implant into the exposed portion of the substrate;

5. The method as set forth in claim 4, wherein:

the forming of at least one bit line comprises forming at least one bit line comprising an n+ region in the exposed portion of the substrate;

the removing of a portion of the first layer of polysilicon is followed by implanting with a tilt angle a p−

pocket into the substrate through the ONO layer; and

the placing of an implant comprises placing a p−

implant into the exposed portion of the substrate.

6. The method as set forth in claim 4, further comprising:

depositing silicon oxynitride on the at least one gate structure and the oxide spacer;

depositing PEOX on the silicon oxynitride;

removing a portion of the deposited PEOX, stopping on the silicon oxynitride; and

removing a portion of the deposited silicon oxynitride to expose the at least one gate structure.

7. The method as set forth in claim 6, further comprising:

depositing a second layer of polysilicon on the silicon oxynitride and the at least one gate structure; and

removing portions of the second layer of polysilicon, the at least one gate structure, and the ONO layer in a direction perpendicular to the reference direction to define a width for at least one memory cell and to expose a portion of the substrate, the portion of the second layer of polysilicon not etched becoming part of the at least one gate structure.

8. The method as set forth in claim 7, further comprising:

depositing a layer of silicon oxynitride on the second layer of polysilicon, on the exposed portions of the substrate, and on sidewalls of the at least one gate structure;

depositing an inter-level dielectric (ILD) to form a flat surface overlying the at least one memory cell; and

removing a portion of the deposited ILD by chemical-mechanical polishing (CMP) and stopping on the silicon oxynitride.

9. The method as set forth in claim 8, further comprising:

forming a contact with the at least one gate structure;

depositing a metal layer; and

removing a portion of the metal layer to define at least one word line that connects to the at least one gate structure along the direction perpendicular to the reference direction.

10. A method for forming an array of trapped charge memory cells, comprising:

providing a semiconductor substrate having an oxide-nitride-oxide (ONO) layer formed on a surface thereof;

depositing a first layer of polysilicon over the ONO layer;

removing a portion of the first layer of polysilicon in a reference direction to form at least one gate structure, thereby exposing a portion of the ONO layer;

implanting with a tilt angle at least one implant pocket into the substrate through the ONO layer;

depositing an oxide spacer on sides of the at least one gate structure and on a portion of the ONO layer;

removing a portion of the ONO layer not covered by the oxide spacer to expose a portion of the substrate; and

forming at least one bit line in the exposed portion of the substrate.

11. The method as set forth in claim 10, wherein the implanting comprises implanting with a tilt angle a plurality of implant pockets into the substrate through the ONO layer.

12. The method as set forth in claim 10, wherein the implanting comprises implanting with a tilt angle a p−

pocket into the substrate through the ONO layer.

13. The method as set forth in claim 10, wherein the implanting comprises implanting with a tilt angle a plurality of p−

pockets into the substrate through the ONO layer.

14. The method as set forth in claim 10, wherein the implanting comprises implanting with a tilt angle a plurality of implant pockets through the ONO layer into the substrate and at least partially beneath the at least one gate structure.

15. The method as set forth in claim 10, wherein the forming of at least one bit line comprises:

placing an n+ implant into the exposed portion of the substrate;

performing an NADP implantation into the exposed portion of the substrate; and

performing a pre-amorphizing implant into the exposed portion of the substrate.

16. The method as set forth in claim 15, further comprising:

depositing silicon oxynitride on the at least one gate structure, the oxide spacer, and the substrate;

depositing PEOX on the silicon oxynitride;

removing a portion of the deposited PEOX by chemical mechanical polishing (CMP), stopping on the silicon oxynitride; and

removing a portion of the deposited silicon oxynitride to expose the at least one gate structure.

17. The method as set forth in claim 16, further comprising:

depositing a second layer of polysilicon on the silicon oxynitride and the at least one gate structure; and

removing portions of the second layer of polysilicon, the at least one gate structure, and the ONO layer in a direction perpendicular to the reference direction to define a width for at least one memory cell and to expose a portion of the substrate, the portion of the second layer of polysilicon not etched becoming part of the at least one gate structure.

18. The method as set forth in claim 17, further comprising:

depositing a layer of silicon oxynitride on the second layer of polysilicon, on the exposed portions of the substrate, and on sidewalls of the at least one gate structure;

depositing an inter-level dielectric (ILD) to form a flat surface overlying the at least one memory cell; and

removing a portion of the deposited ILD by CMP.

19. The method as set forth in claim 18, further comprising:

forming a contact with the at least one gate structure;

depositing a metal layer; and

removing a portion of the metal layer to define at least one word line that connects to the at least one gate structure along the direction perpendicular to the reference direction.