Self-aligned cell integration scheme

• US 20060281256A1
• Filed: 12/20/2005
• Published: 12/14/2006
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: ZEON Corporation
• Original Assignee: Nantero Incorporated
• Inventors: Elmer, James R.B., Carter, Richard J., Burke, Peter A., Gu, Shiqun, Hornback, Verne, Kwak, Byung-Sung, Sun, Sey-Shing, Bhatt, Hemanshu D.
• Granted Patent: US 7,915,122 B2
• Time in Patent Office: Days
• US Class Current: 438/260
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/233 by photolithographic etching
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

Claims

1. A method of forming a self-aligned logic cell, the method comprising the sequential steps of:

forming an electrically conductive bottom electrode,

forming a carbon nanotube layer over the bottom electrode and having electrical continuity with the bottom electrode,

forming an electrically conductive clamp layer over the nanotube layer and having electrical continuity with the nanotube layer, where the clamp layer substantially completely covers the nanotube layer, thereby protecting the nanotube layer,

forming an electrically nonconductive dielectric layer over the clamp layer,

etching the dielectric layer with a first etchant that does not substantially etch the clamp layer, where the clamp layer provides an etch stop to the first etchant and protects the nanotube layer from the first etchant, leaving a remainder of the dielectric layer overlying the bottom electrode,

etching the clamp layer with an isotropic second etchant that does not substantially etch the dielectric layer and the nanotube layer, and which etches the clamp layer underneath a peripheral edge of the dielectric layer to a substantially uniform and desired degree, thereby creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the overlap of the dielectric layer,

forming an electrically conductive spacer layer over at least the nanotube layer that does not substantially underlie the dielectric layer, the spacer layer having electrical continuity with the nanotube layer,

etching the spacer layer to remove all of the spacer layer except a ring portion circumferentially disposed around the peripheral edge of the dielectric layer and overlying a portion of the nanotube layer, and

etching the nanotube layer to remove all of the nanotube layer except those portions of the nanotube layer that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

2. A method of forming a self-aligned logic cell, the method comprising the sequential steps of:

forming an electrically conductive bottom electrode,

forming a carbon nanotube layer over the bottom electrode and having electrical continuity with the bottom electrode,

forming an electrically conductive clamp layer over the nanotube layer and having electrical continuity with the nanotube layer, where the clamp layer substantially completely covers the nanotube layer, thereby protecting the nanotube layer,

forming an electrically nonconductive dielectric layer over the clamp layer, etching the dielectric layer, the clamp layer, and the nanotube layer with a first

etchant to produce a stack of the dielectric layer, the clamp layer, and the nanotube layer remaining over the bottom electrode, where each of the dielectric layer, the clamp layer, and the nanotube layer have substantially equal size after the etch,

etching the dielectric layer with a second etchant that does not substantially etch the clamp layer and the nanotube layer to reduce the size of the dielectric layer and leave a ring portion of the clamp layer exposed around a peripheral edge of the dielectric layer, and

etching the clamp layer with an isotropic third etchant that does not substantially etch the dielectric layer and the nanotube layer, and which etches the clamp layer underneath the peripheral edge of the dielectric layer to a substantially uniform and desired degree, thereby creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer, the overlap of the dielectric layer, and the nanotube layer.