Method and apparatus to reduce latency and improve throughput of input/output data in a processor
First Claim
Patent Images
1. A method comprising:
- receiving at least one packet at an input/output device; and
transferring at least a portion of the packet between a processor and the input/output device without transferring the portion of the packet to a memory device coupled to the processor.
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Accused Products
Abstract
Some embodiments include apparatus and method to transfer data directly between an input/output device and a processor to reduce latency and improve throughput of the processor. Other embodiments are described and claimed.
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Citations
30 Claims
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1. A method comprising:
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receiving at least one packet at an input/output device; and
transferring at least a portion of the packet between a processor and the input/output device without transferring the portion of the packet to a memory device coupled to the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a register circuit to receive at least a portion of the packet from an input/output device; and
a processing unit to process the portion of the packet based on instructions in the processing unit, the processing unit and the register circuit residing on a processor, wherein the portion of the packet is placed directly into the register circuit of the processor, bypassing a memory device coupled to the processor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A system comprising:
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a network interface device to receive at least one packet;
a dynamic random access memory (DRAM) device; and
a processor coupled to the memory device and to the network interface device, the processor including a register circuit to receive at least a portion of the packet, and a processing unit to process the portion of the packet, wherein the portion of the packet is placed directly into the register circuit, bypassing the memory device. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:
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receiving at least one packet at an input/output device; and
transferring at least a portion of the packet between a processor and the input/output device without transferring the portion of packet to a memory device coupled to the processor. - View Dependent Claims (27, 28, 29, 30)
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Specification