Method and apparatus for improving snooping performance in a multi-core multi-processor

• US 20060282622A1
• Filed: 06/14/2005
• Published: 12/14/2006
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Liu, Yen-Cheng, Sistla, Krishnakanth V., Cai, Zhong-Ning
• Granted Patent: US 10,031,848 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache

Abstract

A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where and when an address conflict occurs. Depending upon the timing, a read request or a snoop request may be set for retry. In another embodiment, an age order matrix may be used to determine when several core snoop requests may be issued during a same time period, so that the snoops may be processed during this time period.

Claims

1. A processor, comprising:

a first core;

a second core; and

a scheduler in a bridge to seek an address match from a first memory transaction from a first core to an existing memory transaction from a second core in a content addressable match.

2. The processor of claim 1, wherein said first memory transaction is a read request and said existing memory transaction is a writeback.

3. The processor of claim 2, wherein said scheduler cancels a shared tag update when said address match is found.

4. The processor of claim 2, wherein said scheduler identifies said read request for retry when said address match is found.

5. The processor of claim 1, wherein said first memory transaction is a cross-snoop request and said existing memory transaction is a writeback.

6. The processor of claim 5, wherein said scheduler prevents said cross-snoop request from advancing to a pending state when said address match is found.

7. The processor of claim 5, wherein said scheduler identifies said read request for retry when said address match is found.

8. The processor of claim 1, wherein said first memory transaction is a writeback and said existing memory transaction is a cross-snoop request.

9. The processor of claim 8, wherein said scheduler prevents said cross-snoop request from issuing when said address match is found.

10. The processor of claim 8, wherein said scheduler identifies said read request for retry when said address match is found.

12. The method of claim 11, wherein said first memory transaction is a read request and said previous memory transaction is a writeback, and wherein said identifying includes marking said read request for a retry when said address match is found.

11. A method, comprising:

storing a first memory transaction description from a first core in a searchable memory of a scheduler;

seeking an address match between a previous memory transaction from a second core with said first memory transaction; and

identifying a conflict when said address match is found.

13. The method of claim 11, wherein said first memory transaction is a cross-snoop request and said previous memory transaction is a writeback, and wherein said identifying includes marking said cross-snoop request for a retry when said address match is found.

14. The method of claim 11, wherein said first memory transaction is a writeback and said previous memory transaction is a cross-snoop request, and wherein said identifying includes marking said cross-snoop request for a retry when said address match is found.

15. A system, comprising:

a processor including a first core, a second core, and a scheduler in a bridge to seek an address match from a first memory transaction from a first core to an existing memory transaction from a second core in a content addressable memory;

an external interconnect circuit to send audio data from said processor; and

an audio input/output device to receive said audio data.

16. The system of claim 15, wherein said first memory transaction is a read request and said existing memory transaction is a writeback, and wherein said scheduler identifies said read request for retry when said address match is found.

17. The system of claim 15, wherein said first memory transaction is a cross-snoop request and said existing memory transaction is a writeback, and wherein said scheduler identifies said cross-snoop request for retry when said address match is found.

18. The system of claim 15, wherein first memory transaction is a writeback and said existing memory transaction is a cross-snoop, and wherein said scheduler identifies said cross-snoop request for retry when said address match is found.

19. A processor, comprising:

a first matrix to indicate age of a first snoop request going to a first core;

a second matrix to indicate age of a second snoop request going to a second core; and

a snoop queue to schedule sending said first snoop request and said second snoop request to said first core and said second core using information from said first matrix and said second matrix.

20. The processor of claim 19, wherein said information includes age of all snoop requests in said snoop queue on a per-core basis.

21. The processor of claim 19, wherein said information includes global-ordering information of all snoop requests in said snoop queue on a per-core basis.

22. The processor of claim 19, wherein said snoop queue is further to order returns from said first snoop request and said second snoop request based upon said information.

23. The processor of claim 22, wherein said information includes a determination whether snoop returns have globally-ordered signals set.