Thin film plate phase change RAM circuit and manufacturing method

• US 20060284157A1
• Filed: 06/17/2005
• Published: 12/21/2006
• Est. Priority Date: 06/17/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang Lan, Chen, Shih-Hung
• Granted Patent: US 7,238,994 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

Claims

1. A memory device, comprising:

a programmable memory cell comprising a first electrode having a top surface, a second electrode having a top surface, an insulating member between the first electrode and the second electrode, and a bridge between the first and second electrodes across the insulating member, the bridge having a first side and a second side and contacting the top surfaces of the first and second electrodes on the first side, wherein the bridge comprises memory material having at least two solid phases; and

an isolation device having a terminal beneath the second electrode, and a conductor extending between the terminal and the second electrode.

2. The device of claim 1, wherein the thickness of the insulating member is about 50 nm or less, and said bridge comprises a thin film with a thickness about 50 nm or less and a width about 50 nm or less.

3. The device of claim 1, wherein the thickness of the member is about 20 nm or less, and said bridge comprises a thin film with a thickness about 20 nm or less and a width about 20 nm or less.

4. The device of claim 1, wherein said bridge has a thickness about 10 nm or less and a width about 10 nm or less.

5. The device of claim 1, wherein the first and second electrodes and insulating member comprise elements in a single layer of materials, and the bridge includes a top side and a bottom side and said first side is the bottom side.

6. The device of claim 1, wherein the first and second electrodes and insulating member comprise elements in a single layer of materials having a substantially planar top surface, and the bridge includes a top side and a bottom side, the bottom side contacting the substantially planar top surface of the single layer, whereby said first side is the bottom side.

7. The device of claim 1, wherein the isolation device comprises a transistor.

8. The device of claim 1, wherein the conductor between the terminal and the second electrode comprises a conductive plug in a contact via.

9. The device of claim 1, wherein the terminal comprises a doped region in a semiconductor substrate.

10. The device of claim 1, wherein the isolation device comprises a transistor, and the terminal comprises a doped region in a semiconductor substrate acting as a source or drain of the transistor, and further including a transistor gate structure adjacent the doped region, and over the semiconductor substrate.

11. The device of claim 1, wherein the insulating member comprises silicon nitride.

12. The device of claim 1, wherein the memory material comprises a combination of Ge, Sb, and Te.

13. The device of claim 1, wherein the memory material comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

14. An integrated circuit comprising:

a semiconductor substrate;

a plurality of transistors having terminals including doped regions in the semiconductor substrate, and including components of function circuits adapted to process data; and

an array of programmable memory cells, the programmable memory cells in the array respectively comprising a first electrode having a top surface, a second electrode having a top surface, an insulating member between the first electrode and the second electrode, and a thin film bridge between the first and second electrodes across the insulating member, the bridge having a first side and a second side and contacting the top surfaces of the first and second electrodes on the first side, and wherein the bridge comprises memory material having at least two solid phases;

wherein the plurality of transistors includes components of access circuits for the array of programmable memory cells.

15. The device of claim 14, wherein the thickness of the insulating member is about 50 nm or less, and said bridge comprises a thin film with a thickness about 50 nm or less and a width about 50 nm or less.

16. The device of claim 14, wherein the thickness of the member is about 20 nm or less, and said bridge comprises a thin film with a thickness about 20 nm or less and a width about 20 nm or less.

17. The device of claim 14, wherein said bridge has a thickness about 10 nm or less and a width about 10 nm or less.

18. A memory device, comprising:

a substrate;

an electrode layer on the substrate, the electrode layer including an array of electrode pairs having first electrode having a top surface, a second electrode having a top surface, and an insulating member between the first electrode and the second electrode, and

an array of bridges across the insulating members of respective electrode pairs, the bridges having respective first sides and second sides and contacting the top surfaces of the first and second electrodes in the respective electrode pairs on the first sides, wherein the bridges comprise memory material having at least two solid phases; and

a plurality of bit lines, bit lines in the plurality contacting the first electrodes of memory cells in respective columns of memory cells in the array;

a plurality of bias lines;

a plurality of isolation devices, isolation devices in the plurality having a first terminal coupled to a bias line in the plurality of bias lines, having a second terminal, and having a conductor extending between the second terminal and the first electrode of a corresponding memory cell in the array; and

a plurality of word lines, word lines in the plurality being coupled with isolation devices for memory cells along respective rows in the array, so that control signals on the word lines control connection of memory cells along the respective rows to one of the bias lines in the plurality of bias lines.

19. The device of claim 18, wherein said bias lines in the plurality of bias lines are arranged adjacent corresponding pairs of rows in the array, and two rows of isolation devices in the plurality of isolation devices coupled with said corresponding pairs of rows are coupled to a shared bias line in the plurality of bias lines.

20. The device of claim 18, wherein said bit lines in the plurality of bit lines are arranged along corresponding columns of in the array, and two adjacent memory cells in the corresponding columns share a contact structure for connecting said first electrodes of the two adjacent memory cells to a bit line in the plurality of bit lines.

21. The device of claim 18, wherein the thickness of the insulating member is about 50 nm or less, and said bridge comprises a thin film with a thickness about 50 nm or less and a width about 50 nm or less.

22. The device of claim 18, wherein the thickness of the member is about 20 nm or less, and said bridge comprises a thin film with a thickness about 20 nm or less and a width about 20 nm or less.

23. The device of claim 18, wherein said bridge has a thickness about 10 nm or less and a width about 10 nm or less.

24. A method for manufacturing a memory device, comprising:

forming circuitry in a substrate having a top surface, the circuitry including an array of contacts on the top surface of the substrate;

forming an electrode layer on the substrate, the electrode layer having a top surface, the electrode layer including an array of electrode pairs, including respective first electrodes and second electrodes, and respective insulating members between the first and second electrodes, wherein the second electrodes contact corresponding contacts in the array of contacts, and wherein the first and second electrodes and the insulating members extend to the top surface of the electrode layer, and the insulating members have widths between the first and second electrodes at the top surface;

forming an array of bridges of memory material on the top surface of the electrode layer, the array of bridges including bridges for each of the electrode pairs in the array of electrode pairs, contacting the respective first and second electrodes and extending across the respective insulating members, the bridges comprising films of memory material having a first side and a second side and contacting the respective first and second electrodes on the first side, the bridges defining inter-electrode paths between the first and second electrodes across the insulating members having path lengths defined by the widths of the insulating members, wherein the memory material has at least two solid phases; and

forming a patterned conductive layer over said bridge, and forming an array of contacts between said first electrodes in the array of electrode pairs and said patterned conductive layer.

25. The method of claim 24, wherein said circuitry includes a plurality of word lines and isolation devices controlled by signals on the plurality of word lines, and said patterned conductive layer comprises a plurality of bit lines.

26. The method of claim 24, wherein two electrode pairs in said array of electrode pairs comprise conductive members arranged in a row, including a first conductive member acting as a second electrode in a first of the two electrode pairs, a second conductive member acting as first electrodes in both of the two electrode pairs, and a third conductive member acting as a second electrode in a second of the two electrode pairs.

27. The method of claim 24, wherein the memory material comprises a combination of Ge, Sb, and Te.

28. The method of claim 24, wherein the memory material comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.