SONOS MEMORY DEVICE HAVING CURVED SURFACE AND METHOD FOR FABRICATING THE SAME

• US 20060284245A1
• Filed: 06/15/2006
• Published: 12/21/2006
• Est. Priority Date: 06/18/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Seoul National University Industry Foundation (Seoul National University)
• Original Assignee: Samsung Electronics Co. Ltd., Seoul National University Industry Foundation (Seoul National University)
• Inventors: Lee, Jung-Hoon, Park, Byung-Gook
• Granted Patent: US 7,560,764 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. A radius of curvature of the upper surface of a blocking oxide can be designed to be larger than that of the lower surface of a tunneling oxide, which restrains electrons from passing through the blocking oxide by back-tunneling on erasing. As a result, a SONOS memory device shows an improvement in erasing speed.

Claims

1. A SONOS memory device comprising:

a semiconductor substrate having an active region and a field region;

a gate formed over the active region;

multi-dielectric layers formed between the active region and the gate, wherein the multi-dielectric layers are comprised of a first oxide layer, a nitride layer and a second oxide layer; and

a source region and a drain region formed in the active region under both sides of the gate,

wherein the upper surface of the active region is a curved surface,

the multi-dielectric layers also have a curved shape according to the upper surface of the active region, and

the gate wraps the second oxide layer having the curved shape.

2. The SONOS memory device of claim 1, wherein the curved surface of the active region is a cylindrical surface.

3. The SONOS memory device of claim 1, wherein a radius of curvature of the upper surface of the active region is 50 nm and below.

4. The SONOS memory device of claim 2, wherein a radius of curvature of the upper surface of the active region is 50 nm and below.

5. The SONOS memory device of claim 1, wherein a radius of curvature of the upper surface of the second oxide layer is at least twice that of the upper surface of the active region.

6. The SONOS memory device of claim 2, wherein a radius of curvature of the upper surface of the second oxide layer is at least twice that of the upper surface of the active region.

7. A method for fabricating a SONOS memory device comprising:

a first step of forming a mask for a predetermined active region by depositing an insulating layer on a semiconductor substrate and etching the insulating layer;

a second step of forming a fin-shape active region by etching the semiconductor substrate using the mask, and forming a field region around the active region with an oxide layer;

a third step of planarizing the upper part of the active region and the field region, and etching the oxide layer of the field region in order to expose a part of the fin-shape active region;

a fourth step of an annealing process for making the exposed fin-shape part of the active region cylindrical; and

a fifth step of forming multi-dielectric layers (ONO layers) by depositing a first oxide layer, a nitride layer and a second oxide layer on the cylindrical active region and the field region, and forming a control gate by depositing a gate material on the multi-dielectric layers and etching the gate material.

8. The method of claim 7,

wherein at the first step, the insulating layer is a nitride layer,

at the third step, the planarizing process is accomplished by CMP (Chemical Mechanical Polishing) and the etching process is performed until a part of the mask of the nitride layer is exposed, and

at the fourth step, the annealing process is replaced with an oxidation process for making the upper shape of the active region a cylindrical surface and then etching the nitride layer and a part of the field region to expose the cylindrical surface.

9. The method of claim 7,

wherein at the first step, before the insulating layer is deposited, forming a thin oxide layer on the semiconductor substrate is performed, and then depositing a nitride layer as the insulating layer on the thin oxide layer is performed,

at the second step, before the fin-shape active region is formed, making an upper part of a prearranged active region curved shape is accomplished by an oxidation process, and then etching the substrate by the mask to make the fin-shape active region and forming a field region around the active region with an oxide layer are followed sequentially,

at the third step, the planarizing process is accomplished by CMP, and

at the fourth step, the annealing process is replaced with the oxidation of the second step.

10. The method of claim 7,

wherein at the third step, the planarizing process is accomplished by CMP, and before etching a part of the oxide layer of the field region after the planarizing process, forming a hard mask on the active region is performed, and etching the hard mask and a part of the oxide layer of the field region to expose the fin-shape active region is followed, and

at the fourth step, before the annealing process, removing the hard mask is performed.

11. The method of claim 10,

wherein at the third step, etching the hard mask and a part of the oxide layer of the field region is isotropic, and

at the fourth step, the annealing and removing process of the hard mask is replaced with the etching process of a part of the oxide layer of the field region.

12. The method of claim 7,

wherein before the first step, another step is included, comprising of forming a mask pattern having the same width as the length of a channel by depositing an insulating layer on the semiconductor substrate and etching the insulating layer;

and

performing ion doping for a source and a drain.

13. The method of claim 8,

wherein before the first step, another step is included, comprising of forming a mask pattern having the same width as the length of a channel by depositing an insulating layer on the semiconductor substrate and etching the insulating layer;

and

performing ion doping for a source and a drain.

14. The method of claim 9,

wherein before the first step, another step is included, comprising of forming a mask pattern having the same width as the length of a channel by depositing an insulating layer on the semiconductor substrate and etching the insulating layer;

and

performing ion doping for a source and a drain.

15. The method of claim 10,

wherein before the first step, another step is included, comprising of forming a mask pattern having the same width as the length of a channel by depositing an insulating layer on the semiconductor substrate and etching the insulating layer;

and

performing ion doping for a source and a drain.

16. The method of claim 11,

wherein before the first step, another step is included, comprising of forming a mask pattern having the same width as the length of a channel by depositing an insulating layer on the semiconductor substrate and etching the insulating layer;

and

performing ion doping for a source and a drain.

17. The method of claim 7,

wherein at the fifth step, the etching process for forming a control gate is etching a gate material deposited on the multi-dielectric layers as well as the multi-dielectric layers under the gate material to be etched.

18. The method of claim 8,

wherein at the fifth step, the etching process for forming a control gate is etching a gate material deposited on the multi-dielectric layers as well as the multi-dielectric layers under the gate material to be etched.

19. The method of claim 9,

wherein at the fifth step, the etching process for forming a control gate is etching a gate material deposited on the multi-dielectric layers as well as the multi-dielectric layers under the gate material to be etched.

20. The method of claim 10,

wherein at the fifth step, the etching process for forming a control gate is etching a gate material deposited on the multi-dielectric layers as well as the multi-dielectric layers under the gate material to be etched.

21. The method of claim 11,

wherein at the fifth step, the etching process for forming a control gate is etching a gate material deposited on the multi-dielectric layers as well as the multi-dielectric layers under the gate material to be etched.

22. The method of claim 17,

wherein to the upper active region, the field region and the control gate, exposed by the etching process of the fifth step, an ion implantation process is further included.

23. The method of claim 18,

wherein to the upper active region, the field region and the control gate, exposed by the etching process of the fifth step, an ion implantation process is further included.

24. The method of claim 19,

wherein to the upper active region, the field region and the control gate, exposed by the etching process of the fifth step, an ion implantation process is further included.

25. The method of claim 20,

wherein to the upper active region, the field region and the control gate, exposed by the etching process of the fifth step, an ion implantation process is further included.

26. The method of claim 21,

wherein to the upper active region, the field region and the control gate, exposed by the etching process of the fifth step, an ion implantation process is further included.