MEMORY UTILIZING OXIDE NANOLAMINATES

• US 20060284246A1
• Filed: 07/20/2006
• Published: 12/21/2006
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,433,237 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.

Claims

1. A transistor, comprising:

a first source/drain region

a second source/drain region

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator;

wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; and

circuitry coupled to the source/drain regions to program the transistor in a reverse direction, and read the transistor in a forward direction.

2. The transistor of claim 1, wherein the insulator nanolaminate layers include transition metal oxides.

3. The transistor of claim 2, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

4. The transistor of claim 1, wherein the insulator nanolaminate layers include silicon oxycarbide.

5. The transistor of claim 4, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

6. A vertical memory cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, at least one amorphous charge trapping nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques;

a sourceline coupled to the first source/drain region;

a transmission line coupled to the second source/drain region; and

circuitry coupled to the source/drain regions to program the MOSFET in a reverse direction, and read the MOSFET in a forward direction.

7. The vertical memory cell of claim 6, wherein the insulator nanolaminate layers includes transition metal oxides.

8. The vertical memory cell of claim 7, wherein all the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

9. The vertical memory cell of claim 6, wherein the insulator nanolaminate layers include silicon oxycarbide.

10. The vertical memory cell of claim 9, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

11. The vertical memory cell of claim 6, wherein the first source/drain region of the MOSFET includes a source region and the second source/drain region of the MOSFET includes a drain region.

12. The vertical memory cell of claim 6, further including an electron charge trapped in the amorphous charge trapping nanolaminate layer adjacent the first source/drain region.

13. The vertical memory cell of claim 6, wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

14. A vertical memory cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous;

a wordline coupled to the gate;

a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline;

a bit line coupled to the drain region; and

circuitry coupled to the source/drain regions to program the MOSFET in a reverse direction, and read the MOSFET in a forward direction.

15. The memory cell of claim 14, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

16. The memory cell of claim 14, wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

17. A vertical memory cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, at least one nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques;

a wordline coupled to the gate;

a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline;

a bit line coupled to the drain region; and

circuitry coupled to the source/drain regions to program the MOSFET in a reverse direction, and read the MOSFET in a forward direction.

18. The memory cell of claim 17, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

19. A transistor array, comprising:

a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, and wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous;

a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array;

a number of word lines coupled to the gate of each transistor cell along columns of the memory array;

a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and

circuitry coupled to at least one transistor cell to program the transistor cell in a reverse direction, and read the transistor cell in a forward direction.

20. The transistor array of claim 19, wherein the insulator nanolaminate layers include transition metal oxides.

21. The transistor array of claim 20, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

22. The transistor array of claim 19, wherein the insulator nanolaminate layers include silicon oxycarbide.

23. The transistor array of claim 22, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

24. The transistor array of claim 19, wherein a charge trapped in the charge trapping layer includes a charge adjacent to the source of approximately 100 electrons.

25. The transistor array of claim 19, wherein the first source/drain region of the transistor cell includes a source region and the second source/drain region of the transistor cell includes a drain region.

26. The transistor array of claim 19, wherein the gate insulator of each transistor cell has a thickness of approximately 10 nanometers (nm).

27. The transistor array of claim 19, wherein the number of transistor cells extending from a substrate operate as equivalent to a transistor having a size equal to or less than 1.0 lithographic feature squared (1 F²).

28. A programmable logic array, comprising:

a plurality of input lines for receiving an input signal;

a plurality of output lines; and

one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including;

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; and

wherein the gate insulator includes oxide insulator nanolaminate layers wherein at least one charge trapping layer in the oxide insulator nanolaminate layers is substantially amorphous.

29. The programmable logic array of claim 28, wherein the insulator nanolaminate layers include transition metal oxides.

30. The programmable logic array of claim 29, wherein the insulator nanolaminate layers including transition metal oxides formed by atomic layer deposition (ALD).

31. The programmable logic array of claim 28, wherein the insulator nanolaminate layers include silicon oxycarbide.

32. The programmable logic array of claim 31, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

33. A method for operating a transistor array, comprising:

programming one or more transistors in the array in a reverse direction, wherein each transistor includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, at least one substantially amorphous charge trapping nanolaminate layer formed using atomic layer deposition, wherein the array includes a number of sourcelines coupled to the source regions of each transistor along rows in the array, and wherein the array includes a number of bitlines coupled to the drain region along rows in the array, and wherein programming the one or more transistors in the reverse direction includes;

applying a first voltage potential to a drain region of the transistor;

applying a second voltage potential to a source region of the transistor;

applying a gate potential to a gate of the transistor; and

wherein applying the first, second and gate potentials to the one or more transistors includes creating a hot electron injection into the multilayer gate insulator of the one or more transistors adjacent to the source region such that the one or more transistors become programmed transistors having one of a number of charges trapped in the multilayer gate insulator such that the programmed transistor operates at reduced drain source current in a forward direction.

34. The method of claim 33, wherein applying a first voltage potential to the drain region of the transistor includes grounding the drain region of the transistor.

35. The method of claim 34, wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.

36. The method of claim 35, wherein applying a gate potential to the gate of the transistor includes applying a gate potential to the gate in order to create a conduction channel between the source and drain regions of the transistor.

37. The method of claim 33, wherein the method further includes reading one or more transistors in the array by operating an addressed transistor in a forward direction, wherein operating the transistor in the forward direction includes:

grounding the source region for the addressed transistor;

precharging the drain region for the addressed transistor to a fractional voltage of VDD; and

applying a gate potential of approximately 1.0 Volt to the gate for the addressed transistor such that a conductivity state of the addressed transistor can be compared to a conductivity state of a reference cell.

38. A method for forming a transistor, comprising:

forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;

forming a multilayer gate insulator opposing the channel region, wherein forming the multilayer gate insulator includes forming oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous;

forming a gate over the multilayer gate insulator; and

coupling operation circuitry to the source/drain regions to program the transistor in a reverse direction and to read the transistor in a forward direction.

39. The method of claim 38, wherein forming oxide insulator nanolaminate layers includes forming oxide insulator nanolaminate layers of transition metal oxides.

40. The method of claim 39, wherein forming oxide insulator nanolaminate layers of transition metal oxides includes forming transition metal oxide insulator nanolaminate layers using atomic layer deposition (ALD).

41. The method of claim 38, wherein forming oxide insulator nanolaminate layers includes forming a nanolaminate layer of silicon oxycarbide.

42. The method of claim 41, wherein forming a nanolaminate layer of silicon oxycarbide includes forming a silicon oxycarbide layer using chemical vapor deposition.