Metal gate device with reduced oxidation of a high-k gate dielectric

• US 20060284271A1
• Filed: 06/21/2005
• Published: 12/21/2006
• Est. Priority Date: 06/21/2005
• Status: Active Grant

• Current Assignee: Daedalus Prime LLC (Daedalus Group LLC)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Datta, Suman, Mertz, Matthew V.
• Granted Patent: US 7,501,336 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

Claims

1. A semiconductor device, comprising:

a substrate;

a high-k gate dielectric layer on the substrate;

a metal gate electrode on the high-k gate dielectric layer; and

a capping layer that is substantially free of oxygen and substantially seals a region between the high-k gate dielectric layer and the substrate from structures that comprise oxygen.

2. The device of claim 1, further comprising:

a first set of spacers on either side of the metal gate electrode;

a second set of spacers on either side of the first set of spacers; and

wherein the capping layer is between the first set of spacers and the second set of spacers.

3. The device of claim 2, wherein the second set of spacers have a bottom surface and the capping layer extends beneath the bottom surface of the second set of spacers.

4. The device of claim 1, further comprising a thin oxide layer between the high-k gate dielectric layer and the substrate and a first set of spacers on either side of the metal gate electrode, wherein the first set of spacers have a bottom surface and the thin oxide layer extends beneath the bottom surface of the first set of spacers.

5. The device of claim 1, wherein the capping layer comprises a nitride material.

6. The device of claim 5, wherein the capping layer has a thickness below about 75 angstroms.

7. The device of claim 5, wherein the capping layer comprises a material selected from the group consisting of 8-12% carbon-doped silicon nitride, stoichiometric silicon nitride and silicon carbide.

8. The device of claim 2, wherein the second set of spacers have a bottom surface and the capping layer extends beneath the bottom surface of the second set of spacers.

9. A method for making a semiconductor device, comprising:

forming a high-k gate dielectric layer on a semiconductor substrate;

forming a metal gate electrode on the high-k gate dielectric layer, the metal gate electrode having a first side and a second side;

forming a first set of spacers on the first and second sides of the metal gate electrode; and

forming a capping layer that is substantially free of oxygen on a top surface of the substrate layer, sides of the first set of spacers, and a top surface of the metal gate electrode.

10. The method of claim 9, further comprising:

forming a second set of spacers on the capping layer on the first and second sides of the metal gate electrode; and

removing portions of the capping layer on the top surface of the substrate that extend beyond sides of the second set of spacers.

11. The method of claim 9, further comprising implanting ions into the substrate.

12. The method of claim 11, wherein the capping layer substantially prevents formation of oxide under the high-k gate dielectric layer during the implantation of ions.

13. The method of claim 11, wherein the ions are implanted into the substrate through the capping layer.

14. The method of claim 9, further comprising annealing the substrate after implantation to form source and drain regions.

15. The method of claim 14, further comprising removing portions of the capping layer, wherein the annealing occurs before removing portions of the capping layer.

16. The method of claim 14, wherein the capping layer substantially prevents formation of oxide under the high-k gate dielectric layer during the annealing.

17. The method of claim 9, wherein the capping layer comprises nitride.

19. The method of claim 9, wherein the capping layer has a thickness below about 75 angstroms.

18. The method of claim 18, wherein the capping layer comprises a material selected from the group consisting of 8-12% carbon-doped silicon nitride, stoichiometric silicon nitride and silicon carbide.

20. A method for making a semiconductor device, comprising:

forming a high-k dielectric layer on a thin oxide layer on a substrate;

forming a metal gate electrode on the high-k dielectric layer; and

forming an oxygen barrier layer that is substantially free of oxygen to prevent the thin oxide layer from contacting an oxygen source.

21. The method of claim 20, further comprising forming spacers on the oxygen barrier layer on either side of the metal gate electrode after forming the oxygen barrier layer.

22. The method of claim 21, further comprising removing portions of the oxygen barrier layer that are on a top surface of the substrate and extend beyond sides of the spacers.

23. The method of claim 20, wherein the oxygen barrier layer comprises a material selected from a group consisting of 8-12% carbon-doped silicon nitride, stoichiometric silicon nitride and silicon carbide.

24. The method of claim 20, wherein the oxygen barrier layer has a thickness below about 75 angstroms.

25. The method of claim 20, further comprising:

implanting ions into the substrate on either side of the metal gate electrode to form source and drain regions; and

annealing the source and drain regions after forming the oxygen barrier layer.