Initiation of differential link retraining upon temperature excursion

• US 20060284733A1
• Filed: 06/20/2005
• Published: 12/21/2006
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ruff, Klaus, Shykind, David, McCall, James A.
• Granted Patent: US 7,246,022 B2
• Time in Patent Office: Days
• US Class Current: 340/584
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.

Claims

1. A method comprising:

detecting a change in temperature in an integrated circuit that is coupled to a differential communication link;

responding to said detected change in temperature by initiating a retraining process for said differential communication link; and

performing the initiated retraining process;

wherein the retraining process includes retraining logic that is part of the integrated circuit interacting with a phase interpolator to adjust a phase of a clock signal output from the phase interpolator, the phase interpolator being part of the integrated circuit.

2. The method of claim 1, wherein the retraining logic that is part of said integrated circuit initiates said retraining process.

3. The method of claim 2, further comprising:

gating off, during said retraining process, at least some components of said integrated circuit that are not required for said retraining process.

4. The method of claim 1, wherein retraining logic that is part of another integrated circuit coupled to said differential communication link initiates said retraining process.

5. The method of claim 1, wherein said detecting includes detecting an output of a thermal diode that is included in said integrated circuit.

6. An integrated circuit comprising:

an input/output (I/O) block to couple to a differential communication link;

a thermal diode to indicate a change in temperature in the integrated circuit;

a monitor block to read an output of said thermal diode;

retraining logic included in said I/O block and coupled to said monitor block, said retraining logic to control said I/O block to perform a retraining process in response to said monitor block detecting said change of temperature indicated by said thermal diode; and

a phase interpolator included in said I/O block;

wherein the retraining process includes the retraining logic interacting with the phase interpolator to adjust a phase of a clock signal output from the phase interpolator.

7. The integrated circuit of claim 6, wherein said retraining logic includes a timer to cause said retraining logic to control said I/O block to perform said retraining process at regular intervals if said change in temperature does not occur.

8. The integrated circuit of claim 6, wherein said retraining logic is operative to cause said I/O block to perform said retraining process in response to a signal received by said I/O block from another integrated circuit coupled to said differential communication link, said signal to indicate a change of temperature in said another integrated circuit.

9. The integrated circuit of claim 6, wherein the integrated circuit is a memory controller.

10. A system comprising:

a memory controller;

a dynamic random access memory (DRAM); and

a differential communication link to which said memory controller and said DRAM are coupled;

wherein said memory controller includes;

an input/output (I/O) block coupled to said differential communication link;

a thermal diode to indicate a change of temperature in the memory controller;

a monitor block to read an output of said thermal diode;

retraining logic included in said I/O block and coupled to said monitor block, said retraining logic to control said I/O block to perform a retraining process in response to said monitor block detecting said change of temperature indicated by said thermal diode; and

a phase interpolator included in said I/O block;

wherein the retraining process includes the retraining logic interacting with the phase interpolator to adjust a phase of a clock signal output from the phase interpolator.

11. The system of claim 10, wherein said retraining logic includes a timer to cause said retraining logic to control said I/O block to perform said retraining process at regular intervals if said change in temperature does not occur.

12. The system of claim 10, wherein the DRAM includes a thermal diode to indicate a change of temperature in the DRAM, the DRAM operative to transmit to the memory controller, via the differential communication link, a signal to indicate said change of temperature in the DRAM, the retraining logic operative to respond to said signal by controlling said I/O block to perform said retraining process.

13. The system of claim 10, further comprising:

a circuit board on which said memory controller and said DRAM are mounted.

14. The system of claim 10, wherein the memory controller is operative to gate off, during said retraining process, at least some components of said memory controller that are not required for said retraining process.

15. The system of claim 10, further comprising:

a second differential communication link coupled to said memory controller; and

a second DRAM coupled to said second differential communication link.

16-18. -18. (canceled)

19. A method comprising:

detecting a change of temperature in a first integrated circuit;

sending a signal from said first integrated circuit to a second integrated circuit, said signal to indicate said detected change of temperature, said sending including sending said signal to said second integrated circuit via a differential communication link;

responding to said signal by initiating a retraining process for said differential communication link; and

performing the initiated retraining process;

wherein the retraining process includes retraining logic that is part of the second integrated circuit interacting with a phase interpolator to adjust a phase of a clock signal output from the phase interpolator, the phase interpolator being part of the second integrated circuit; and

wherein said first integrated circuit is a dynamic random access memory (DRAM) device and said second integrated circuit is a memory controller.