Programmable dual input switched-capacitor gain stage

• US 20060284754A1
• Filed: 06/15/2005
• Published: 12/21/2006
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Braswell, Brandt, Garrity, Douglas A., Locascio, David R.
• Granted Patent: US 7,307,572 B2
• Time in Patent Office: Days
• US Class Current: 341/172
• CPC Class Codes: H03M 1/1225 using time-division multiplexing
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Claims

1. A switched-capacitor gain stage comprising:

a plurality of input nodes for a plurality of input voltage signals;

an amplifier having an amplifier input node and an amplifier output node;

a plurality of switched-capacitor arrangements, each being coupled between one of said input nodes and said amplifier input node such that each of said input nodes is coupled to a like number of said switched-capacitor arrangements; and

a switch architecture configured to cause said switched-capacitor gain stage to concurrently sample said input voltage signals, and to provide, at said amplifier output node, a series of interleaved output voltage samples derived from said input voltage signals.

2. A switched-capacitor gain stage according to claim 1, each of said switched-capacitor arrangements comprising:

a first capacitor having a first input end and a first output end; and

a second capacitor having a second input end and a second output end connected to said first output end of said first capacitor;

wherein

said switch architecture is configured to connect said first input end and said second input end to a respective one of said input nodes, and to connect said first output end and said second output end to a reference potential for input voltage signal sampling.

3. A switched-capacitor gain stage according to claim 2, said reference potential being a ground.

4. A switched-capacitor gain stage according to claim 1, at least one of said switched-capacitor arrangements comprising a programmable capacitance.

5. A switched-capacitor gain stage according to claim 1, each of said switched-capacitor arrangements comprising two capacitors having equal capacitance.

6. A switched-capacitor gain stage according to claim 5, wherein input loading at each of said input nodes is balanced.

7. A switched-capacitor gain stage according to claim 1, each of said switched capacitor arrangements comprising:

a first capacitor having a first output end; and

a second capacitor having a second input end and a second output end connected to said first output end of said first capacitor;

wherein

said switch architecture is configured to connect said first capacitor between said amplifier input node and said amplifier output node, to connect said second output end to said amplifier input node, and to connect said second input end to a reference voltage for output voltage generation.

8. A switched-capacitor gain stage according to claim 7, said reference voltage being a programmable voltage value.

9. A switched-capacitor gain stage according to claim 8, said reference voltage being selectable between a positive reference voltage value, zero, and a negative reference voltage value.

10. A switched-capacitor gain stage according to claim 1, further comprising a plurality of comparison and digital logic architectures, each being coupled to a respective input node to receive a respective input voltage signal, and each being configured to generate a respective digital output corresponding to said respective input voltage signal.

11. A switched-capacitor gain stage comprising:

an amplifier having an amplifier input node and an amplifier output node;

a first switched-capacitor arrangement having an input node for receiving a first input voltage signal, an output node coupled to said amplifier output node, and a feedback node coupled to said amplifier input node;

a second switched-capacitor arrangement having an input node for receiving a second input voltage signal, an output node coupled to said amplifier output node, and a feedback node coupled to said amplifier input node;

a third switched-capacitor arrangement having an input node for receiving said first input voltage signal, an output node coupled to said amplifier output node, and a feedback node coupled to said amplifier input node;

a fourth switched-capacitor arrangement having an input node for receiving said second input voltage signal, an output node coupled to said amplifier output node, and a feedback node coupled to said amplifier input node; and

a switch architecture configured to cause said switched-capacitor gain stage to concurrently sample said first input signal and said second input signal, and to provide, at said amplifier output node, a series of interleaved output voltage samples derived from said first input voltage signal and said second input voltage signal.

12. A switched-capacitor gain stage according to claim 11, each of said switched-capacitor arrangements comprising:

a first capacitor having a first input end and a first output end; and

a second capacitor having a second input end and a second output end connected to said first output end of said first capacitor;

wherein

said switch architecture is configured to connect said first input end and said second input end to a respective one of said input nodes, and to connect said first output end and said second output end to a reference potential for input voltage signal sampling.

13. A switched-capacitor gain stage according to claim 11, each of said switched capacitor arrangements comprising:

a first capacitor having a first output end; and

a second capacitor having a second input end and a second output end connected to said first output end of said first capacitor;

wherein

said switch architecture is configured to connect said first capacitor between said amplifier input node and said amplifier output node, to connect said second output end to said amplifier input node, and to connect said second input end to a reference voltage for output voltage generation.

14. A switched-capacitor gain stage according to claim 11, further comprising:

a first comparison and digital logic architecture coupled to said input node of said first switched-capacitor arrangement and to said input node of said third switched-capacitor arrangement, said first comparison and digital logic architecture being configured to receive said first input voltage signal and to generate a first digital output corresponding to said first input voltage signal; and

a second comparison and digital logic architecture coupled to said input node of said second switched-capacitor arrangement and to said input node of said fourth switched-capacitor arrangement, said second comparison and digital logic architecture being configured to receive said second input voltage signal and to generate a second digital output corresponding to said second input voltage signal.

15. A switched-capacitor gain stage according to claim 11, said switch architecture being configured to perform switching at a first time, comprising:

switching said first switched-capacitor arrangement to sample said first input voltage signal;

switching said second switched-capacitor arrangement to sample said second input voltage signal;

switching said third switched-capacitor arrangement to hold its previously-sampled voltage; and

switching said fourth switched-capacitor arrangement for coupling to said amplifier and to a selectable reference voltage for output voltage generation.

16. A method of operating a switched-capacitor gain stage having a first input node, a second input node, an amplifier, first, second, third, and fourth switched-capacitor arrangements, and a switch architecture for selectively coupling the first, second, third, and fourth switched-capacitor arrangements to the first input node, the second input node, and the amplifier, said method comprising:

at a first time, switching the first switched-capacitor arrangement and the second switched-capacitor arrangement to sample a first input voltage signal present at the first input node and a second input voltage signal present at the second input node, respectively, switching the third switched-capacitor arrangement to hold its previously-sampled voltage, and switching the fourth switched-capacitor arrangement for coupling to the amplifier and a selectable reference voltage for output voltage generation.

17. A method according to claim 16, wherein switching the fourth switched-capacitor arrangement at said first time provides an amplifier output voltage based upon a past-sampled voltage stored by the fourth switched-capacitor arrangement, and based upon said selectable reference voltage.

18. A method according to claim 16, further comprising:

at a second time subsequent to said first time, switching the first switched-capacitor arrangement for coupling to the amplifier and said selectable reference voltage for output voltage generation, switching the second switched-capacitor arrangement to hold its previously-sampled voltage, switching the third switched-capacitor arrangement to hold its previously-sampled voltage, and switching the fourth switched-capacitor arrangement to hold its previously-sampled voltage.

19. A method according to claim 18, further comprising:

at a third time subsequent to said second time, switching the first switched-capacitor arrangement to hold its previously-sampled voltage, switching the second switched-capacitor arrangement for coupling to the amplifier and said selectable reference voltage for output voltage generation, and switching the third switched-capacitor arrangement and the fourth switched-capacitor arrangement to sample said first input voltage signal present at the first input node and said second input voltage present at the second input node, respectively.

20. A method according to claim 19, further comprising:

at a fourth time subsequent to said third time, switching the first switched-capacitor arrangement to hold its previously-sampled voltage, switching the second switched-capacitor arrangement to hold its previously-sampled voltage, switching the third switched-capacitor arrangement for coupling to the amplifier and said selectable reference voltage for output voltage generation, and switching the fourth switched-capacitor arrangement to hold its previously-sampled voltage.