Driving circuit for organic light emitting diode, display device using the same and driving method of organic light emitting diode display device

• US 20060284801A1
• Filed: 12/02/2005
• Published: 12/21/2006
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Yoon, Soo Young, Chun, Min Doo
• Granted Patent: US 7,675,493 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

An organic light emitting diode drive circuit includes an organic light emitting diode which emits light with a current, a first transistor, a second transistor and a stress compensation circuit. The first transistor supplies a data voltage to a first node in response to a scan pulse. The second transistor controls a current flowing in the organic light emitting diode by the data voltage on the first node. The stress compensation circuit discharges the first node in response to a reset pulse. The organic light emitting diode driving circuit is adaptive to compensate characteristic changes of the organic light emitting diode drive circuit.

Claims

1. An organic light emitting diode drive circuit, comprising:

an organic light emitting diode that emits light with a current;

a first switch supplying a data voltage to a first node in response to a scan pulse;

a second switch controlling the current flowing in the organic light emitting diode; and

a stress compensation circuit that controls the data voltage at the first node.

2. The organic light emitting diode drive circuit according to claim 1, wherein the stress compensation circuit includes a third switch that discharges the data voltage at the first node in response to a reset pulse.

3. The organic light emitting diode drive circuit according to claim 2, wherein generation of the reset pulse is delayed by a ½

frame period from generation of the scan pulse.

4. The organic light emitting diode drive circuit according to claim 2, wherein the data voltage rises from a first low potential reference voltage, and the scan pulse and the reset pulse rise from a second low potential reference voltage, the second low potential reference voltage configured to be lower than the first low potential reference voltage.

5. The organic light emitting diode drive circuit according to claim 2, wherein the data voltage rises from a first low potential reference voltage, and the reset pulse rise from a second low potential reference voltage, the second low potential reference voltage configured to be lower than the first low potential reference voltage.

6. The organic light emitting diode drive circuit according to claim 2, wherein the first to third switches comprises first to third transistors.

7. The organic light emitting diode drive circuit according to claim 6, wherein the first to third transistors are configured to be amorphous silicon transistors.

8. The organic light emitting diode drive circuit according to claim 6, wherein the first to third transistors are configured to be polysilicon transistors.

9. The organic light emitting diode drive circuit according to claim 1, wherein the stress compensation circuit supplies a compensation voltage to the first node, and a polarity of the compensation voltage is different from a polarity of the data voltage at the first node.

10. The organic light emitting diode drive circuit according to claim 9, wherein the stress compensation circuit includes a third switch supplying to the first node a voltage that is lower than a low potential reference voltage of the data voltage.

11. The organic light emitting diode drive circuit according to claim 10, wherein the third switch is configured to be turned on subsequent to the first switch.

12. The organic light emitting diode drive circuit according to claim 10, wherein the first to third switches comprise first to third transistors and the first to third transistors are configured to be amorphous silicon transistors.

13. The organic light emitting diode drive circuit according to claim 10, wherein the first to third transistors comprise first to third transistors and the first to third transistors are configured to be polysilicon transistors.

14. An organic light emitting diode display device, comprising:

data lines and gate lines that intersect each other;

a gate drive circuit supplying a scan pulse to the gate lines;

a data drive circuit supplying a video data voltage to the data lines;

an organic light emitting diode that emits light with a current; and

an organic light emitting diode drive circuit including;

a first switch supplying the video data voltage to a first node in response to the scan pulse;

a second switch controlling a current flowing in the organic light emitting diode in response to the video data voltage at the first node; and

a stress compensation circuit that controls the video data voltage at the first node.

15. The organic light emitting diode display device according to claim 14, wherein the stress compensation circuit comprises a third switch that discharges the video data voltage at the first node in response to a reset pulse.

16. The organic light emitting diode display device according to claim 15, wherein generation of the reset pulse is delayed by a designated time from generation of the scan pulse.

17. The organic light emitting diode display device according to claim 16, wherein the generation of the reset pulse is delayed by a ½

frame period from the generation of the scan pulse.

18. The organic light emitting diode display device according to claim 15, wherein the first to third switches comprises first to third transistors and the first to the third transistors are configured to be amorphous silicon transistors.

19. The organic light emitting diode display device according to claim 15, wherein the first to third switches comprises first to third transistors and the first to third transistors are configured to be polysilicon transistors.

20. The organic light emitting diode display device according to claim 14, wherein the stress compensation circuit includes a third switch that discharges the first node in response to a reset pulse, and the data voltage rises from a first low potential reference voltage.

21. The organic light emitting diode display device according to claim 20, wherein the scan pulse and the reset pulse, or the reset pulse alone rise from a second low potential reference voltage, and the second low potential reference voltage is lower than the first low potential reference voltage.

22. The organic light emitting diode display device according to claim 21, wherein generation of the reset pulse is delayed by a ½

frame period from generation of the scan pulse.

23. An organic light emitting diode display device according to claim 14, wherein the stress compensation circuit supplies a compensation voltage to the first node, and a polarity of the compensation voltage is different from a polarity of the data voltage at the first node.

24. The organic light emitting diode display device according to claim 23, wherein the stress compensation circuit comprises a third switch, and the third switch is turned on subsequent to the first switch in response to a reset pulse such that a voltage lower than a low potential reference voltage of the data voltage is supplied to the first node.

25. The organic light emitting diode display device according to claim 24, wherein generation of the reset pulse is delayed by a ½

frame period from generation of the scan pulse.

26. A driving method of an organic light emitting diode display device, comprising:

supplying a scan pulse to a plurality of gate lines;

supplying a data voltage to a plurality of data lines configured to intersect the gate lines; and

controlling a voltage at a driving transistor of an organic light emitting diode drive circuit with application of a reset voltage.

27. The driving method according to claim 26, wherein controlling the voltage comprises applying the reset voltage to a plurality of reset lines, a reset line connected to the driving transistor at a node.

28. The driving method according to claim 27, wherein controlling the voltage comprises charging the node of the driving transistor with the voltage during a half period of a frame and discharging the voltage during a next half period of the frame.

29. The driving method according to claim 28, wherein controlling the voltage comprises applying the data voltage to the node of the driving transistor during a half period of a frame and applying the reset voltage to the node during a next half period of the frame, the data voltage and the reset voltage having opposite polarities.

30. The driving method according to claim 29, further comprising:

rising the data voltage from a first low potential reference voltage; and

rising the reset voltage from a second low potential reference voltage lower than the first low potential reference voltage.