Selective slow programming convergence in a flash memory device

• US 20060285392A1
• Filed: 05/01/2006
• Published: 12/21/2006
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Incarnati, Michele, Vali, Tommaso, Santin, Giovanni
• Granted Patent: US 7,324,383 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells

Abstract

A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the V_t of the cell. The other cells continue to be programmed at their normal pace. As the V_t for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.

Claims

1. A method for selectively slow programming convergence in a memory device comprising an array of memory cells having rows coupled by word lines and columns coupled by bit lines, the method comprising:

increasing a threshold voltage for each of a plurality of memory cells; and

selectively biasing bit lines coupled to the plurality of memory cells such that a bit line is only biased when the threshold voltage of an associated memory cell reaches a first verify threshold voltage of two verify threshold voltages, the first verify threshold voltage being less than the second verify threshold voltage.

2. The method of claim 1 wherein increasing the threshold voltage comprises generating a plurality of programming pulses on a predetermined word line coupled to the memory cell being programmed.

3. The method of claim 1 and further including continuing to program memory cells having a threshold voltage below the first verify threshold voltage.

4. The method of claim 1 and further including performing a verify operation to determine the threshold voltage for each memory cell being programmed.

5. The method of claim 1 wherein the memory device comprises a flash memory device.

6. The method of claim 5 wherein the flash memory device is one of a NAND—

type flash memory or a NOR—

type flash memory.

7. The method of claim 1 wherein the second verify threshold voltage is a threshold voltage at which the memory cell is considered to be programmed.

8. The method of claim 1 wherein the threshold voltage is part of a threshold voltage distribution indicating one of a plurality of possible multilevel states programmable into the memory cell.

9. A method for selectively slow programming convergence in a flash memory device comprising a matrix of memory cells having rows coupled by word lines and columns coupled by bit lines, the method comprising:

performing a programming operation on each of a plurality of memory cells;

performing a verify operation on each of the plurality of memory cells to determine its respective threshold voltage; and

selectively biasing bit lines coupled to the plurality of memory cells such that a bit line is only biased with a first bit line bias voltage when the threshold voltage of an associated memory cell reaches a first verify threshold voltage of two verify threshold voltages, the first verify threshold voltage being less then the second verify threshold voltage, the first bit line bias voltage being greater than 0V and less than a supply voltage.

10. The method of claim 9 wherein performing the programming operation comprises generating a plurality of programming voltage pulses that increase incrementally by a step voltage.

11. The method of claim 9 and further including selectively biasing bit lines, coupled to the plurality of memory cells, with an inhibit voltage in response to a memory cell associated with the bit line having a threshold voltage at least equal to the second verify threshold voltage.

12. The method of claim 11 wherein the inhibit voltage is the supply voltage.

13. A memory device comprising:

an array of memory cells arranged in rows and columns such that the rows are coupled by word lines and the columns are coupled by bit lines, each memory cell having an associated threshold voltage; and

control circuitry that controls programming of the array of memory cells, the control circuitry adapted to control generation of a plurality of programming pulses to increase the associated threshold voltages of a set of memory cells to be programmed, the control circuitry further adapted to selectively control biasing of only a bit line associated with a memory cell having a threshold voltage that is equal to or greater than a first verify threshold voltage but less than a second verify threshold voltage.

14. The device of claim 13 wherein the array of memory cells is comprised of floating gate field effect transistors.

15. The device of claim 13 wherein a threshold voltage that is equal to or greater than the second verify threshold voltage is indicative of a programmed memory cell.

16. The device of claim 13 wherein the control circuitry is further adapted to control generation of additional programming pulses, increasing by a predetermined step voltage from a previous programming pulse, in response to threshold voltages that are less than the second verify threshold voltage.

17. The device of claim 13 wherein the memory device is a NAND flash memory device.

18. The device of claim 13 wherein the control circuitry is further adapted to bias, at 0V, all bit lines associated with memory cells having threshold voltages that have not yet reached the first verify threshold voltage.

19. A memory system comprising:

a processor that generates memory program signals; and

a memory device coupled to the processor that operates in response to the memory program signals, the device comprising;

an array of memory cells arranged in rows and columns such that the rows are coupled by word lines and the columns are coupled by bit lines, each memory cell having an associated threshold voltage; and

control circuitry that controls programming of the array of memory cells, the control circuitry adapted to control generation of a plurality of programming pulses to increase the associated threshold voltages of a set of memory cells to be programmed, the control circuitry further adapted to selectively control biasing of only a bit line associated with a memory cell having a threshold voltage that is equal to or greater than a first verify threshold voltage but less than a second verify threshold voltage.

20. A method for selectively slow programming convergence in a flash memory device comprising a matrix of memory cells having rows coupled by word lines and columns coupled by bit lines, the method comprising:

performing a programming operation on each of a set of multilevel memory cells, each memory cell of the set having a threshold voltage distribution, the programming operation comprising a plurality of programming pulses that increase incrementally from a previous pulse and are applied to each word line coupled the set of memory cells, the threshold voltage distribution increasing in response to each programming pulse;

performing a verify operation, after each programming pulse, on each memory cell to determine its respective threshold voltage distribution;

selectively biasing, with a first bias voltage, only each bit line that is associated with a memory cell having maximum voltage in its threshold voltage distribution that is equal to or greater than a pre-verify threshold voltage and less than a verify threshold voltage, the first bias voltage being greater than 0V and less than a supply voltage; and

selectively biasing, with an inhibit voltage, only each bit line that is associated with a memory cell having the maximum voltage in the threshold voltage that is at least equal to the verify threshold voltage.

21. The method of claim 20 wherein the first bias voltage comprises a voltage in a range of 0.5 to 0.9V.

22. The method of claim 20 wherein the inhibit voltage is substantially equal to V_CC.

23. The method of claim 20 wherein the threshold voltage distribution indicates one of a plurality of states programmed into the memory cell.

24. The method of claim 23 wherein the plurality of states comprise two bits of data.