PROGRAM METHOD WITH OPTIMIZED VOLTAGE LEVEL FOR FLASH MEMORY

• US 20060285396A1
• Filed: 06/17/2005
• Published: 12/21/2006
• Est. Priority Date: 06/17/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ha, Chang Wan
• Granted Patent: US 7,239,557 B2
• Time in Patent Office: Days
• US Class Current: 365/185.330
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory.

Claims

1. A method of operating a non-volatile memory device, comprising:

calculating a number of expected data bits from program data to be programmed into a non-volatile memory array in a program operation;

calculating a number of failed data bits that failed to program in the program operation; and

increasing a programming voltage in response to comparison of the number of expected data bits and the number of failed data bits.

2. The method of claim 1, wherein increasing a programming voltage in response to comparison of the number of expected data bits and the number of failed data bits further comprises increasing a programming voltage in response to the percentage of the expected data bits that failed to correctly program into the non-volatile memory array during the programming operation.

3. The method of claim 1, further comprising:

disabling programming of one or more memory cells that correctly programmed; and

applying the increased programming voltage to program one or more bits of the data that failed to program correctly.

4. The method of claim 1, further comprising:

repeating for one or more iteration cycles,

calculating a number of expected data bits from program data to be programmed into a non-volatile memory array in a program operation;

calculating a number of failed data bits that failed to program in the program operation; and

increasing a programming voltage in response to comparison of the number of expected data bits and the number of failed data bits.

5. The method of claim 4, wherein repeating for one or more iteration cycles further comprises iterating until a maximum number of iterations is reached or the number of failed data bits is zero.

6. The method of claim 1, wherein increasing a programming voltage in response to comparison of the number of expected data bits and the number of failed data bits further comprises increasing a programming voltage in response to comparison of the number of expected data bits and the number of failed data bits, where the overall increase in programming voltage is limited by a specified maximum programming voltage level.

7. The method of claim 1, further comprising:

profiling the non-volatile memory device to determine a profile of a programming voltage increase for a given comparison of the number of expected data bits and the number of failed data bits.

8. The method of claim 7, wherein profiling the non-volatile memory device to determine a profile of a programming voltage increase for a given comparison of the number of expected data bits and the number of failed data bits further comprises profiling the non-volatile memory device by one of profiling the non-volatile memory device to determine a profile of a programming voltage increase for a given comparison of the number of expected data bits and the number of failed data bits for the non-volatile memory device manufacturing process, characterizing the non-volatile memory device design, profiling the non-volatile memory device to determine a profile of a programming voltage increase for a given comparison of the number of expected data bits and the number of failed data bits for a specific memory device, profiling the non-volatile memory device to determine a profile of a programming voltage increase for a given comparison of the number of expected data bits and the number of failed data bits for a specific memory array area, and profiling the non-volatile memory device to determine a profile of a programming voltage increase for a given comparison of the number of expected data bits and the number of failed data bits for a specific memory cell wear level.

9. The method of claim 1, wherein the non-volatile memory device is one of a Flash memory device, a EEPROM memory device, a Polymer Memory device, a Ferroelectric Random Access Memory (FeRAM) device, an Ovionics Unified Memory (OUM) device, and Magnetoresistive Random Access Memory (MRAM) device.

10. The method of claim 1, wherein the non-volatile memory array is one of a NAND architecture memory array and a NOR architecture memory array.

11. A method of operating a non-volatile memory device, comprising:

programming a plurality of data bits into a non-volatile memory array of the non-volatile memory device in a programming cycle by applying an initial programming voltage to a plurality of memory cells that are selected to be programmed with the plurality of data bits;

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle;

disabling programming of one or more memory cells that correctly programmed; and

applying the increased programming voltage to program one or more bits of the data that failed to program correctly.

12. The method of claim 11, further comprising:

repeating for one or more iteration cycles,

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle;

disabling programming of one or more memory cells that correctly programmed; and

applying the increased programming voltage to program one or more bits of the data that failed to program correctly.

13. The method of claim 12, wherein repeating for one or more iteration cycles further comprises iterating the loop of increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle, disabling programming of one or more memory cells that correctly programmed, and applying the increased programming voltage to program one or more bits of the data that failed to program correctly, until a maximum number of iterations is reached.

14. The method of claim 12, wherein increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle further comprises increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle, where the increase in programming voltage is limited by a specified maximum programming voltage level.

15. The method of claim 11, further comprising:

profiling the non-volatile memory device to specify the desired programming voltage delta/increase for a given failing percentage of data bits.

16. The method of claim 15, wherein profiling the non-volatile memory device to specify the desired programming voltage delta/increase for a given failing percentage of data bits further comprises profiling the non-volatile memory device by one of characterizing the non-volatile memory device manufacturing process, characterizing the non-volatile memory device design, characterizing a specific memory device, characterizing a specific memory array area, and characterizing a specific memory cell wear level to select profile for the desired programming voltage delta/increase for a given failing percentage of data bits.

17. The method of claim 11, wherein the non-volatile memory device is one of a Flash memory device, a EEPROM memory device, a Polymer Memory device, a Ferroelectric Random Access Memory (FeRAM) device, an Ovionics Unified Memory (OUM) device, and Magnetoresistive Random Access Memory (MRAM) device.

18. The method of claim 11, wherein the non-volatile memory array is one of a NAND architecture memory array and a NOR architecture memory array.

19. A method of programming data, comprising:

receiving a programming command and program data containing a plurality of data bits;

programming the plurality of data bits into a non-volatile memory array in a programming cycle by applying an initial programming voltage to a plurality of memory cells that are selected to be programmed with the plurality of data bits; and

attempting to program any memory cells of the plurality of memory cells that failed to program correctly by,

verifying the plurality of data bits of program data programmed into the plurality of memory cells of the non-volatile memory array,

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells,

disabling programming of one or more memory cells that correctly programmed,

applying the increased programming voltage to program one or more bits of the data that failed to program correctly, and

repeating for one or more iteration cycles.

20. The method of claim 19, wherein repeating for one or more iteration cycles further comprises repeating for one or more iteration cycles, until none of the plurality of data bits fail to verify or a maximum number of iterations is reached.

21. The method of claim 19, wherein increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle further comprises limiting a total programming voltage level to a specified maximum programming voltage level.

22. The method of claim 19, further comprising:

profiling the non-volatile memory array to specify the desired programming voltage delta/increase for a given failing percentage of data bits.

23. The method of claim 22, wherein profiling the non-volatile array to specify the desired programming voltage delta/increase for a given failing percentage of data bits further comprises profiling the non-volatile memory array by one of characterizing the non-volatile memory array manufacturing process, characterizing the non-volatile memory array design, characterizing a specific memory array, characterizing a specific memory array area, and characterizing a specific memory cell wear level to select profile for the desired programming voltage delta/increase for a given failing percentage of data bits.

24. A method of profiling a non-volatile memory device comprising:

profiling the non-volatile memory device to specify the desired programming voltage delta increase for subsequent programming cycles for a given failing percentage of data bits that are being programmed into the non-volatile memory device.

25. The method of claim 24, wherein profiling the non-volatile memory device to specify the desired programming voltage delta increase for subsequent programming cycles for a given failing percentage of data bits that are being programmed into the non-volatile memory device further comprises profiling the non-volatile memory device by one of characterizing the non-volatile memory device manufacturing process, characterizing the non-volatile memory device design, characterizing a specific memory array, characterizing a specific memory array area, and characterizing a specific memory cell wear level to select profile for the desired programming voltage delta/increase for a given failing percentage of data bits.

26. A method of operating a Flash memory device, comprising:

receiving a programming command and program data containing a plurality of data bits on an interface of the Flash memory device;

transferring the program data to a data cache;

transferring the program data to a write data latch;

calculating the number of bits to be programmed in the program data held in the data cache;

programming the plurality of data bits into a Flash memory array in a programming cycle by applying an initial programming voltage to a plurality of memory cells that are selected to be programmed with the plurality of data bits; and

attempting to program any memory cells of the plurality of memory cells that failed to program correctly by,

verifying the plurality of data bits of program data programmed into the plurality of memory cells of the Flash memory array,

calculating the number of memory cells that failed to program correctly,

calculating a percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells in relation to the number of bits to be programmed held in the data cache,

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells,

disabling programming of one or more memory cells that correctly programmed,

applying the increased programming voltage to program one or more bits of the data that failed to program correctly, and

repeating for one or more iteration cycles.

27. The method of claim 26, wherein the Flash memory device is one of a NAND architecture Flash memory device and a NOR architecture Flash memory device.

28. The method of claim 26, wherein repeating for one or more iteration cycles further comprises repeating for one or more iteration cycles, until none of the plurality of data bits fail to verify or a maximum number of iterations is reached.

29. The method of claim 26, wherein increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the Flash memory array during the programming cycle further comprises limiting a total programming voltage level to a specified maximum programming voltage level.

30. The method of claim 26, further comprising:

profiling the Flash memory array to specify the desired programming voltage delta increase for a given failing percentage of data bits.

31. The method of claim 30, wherein profiling the Flash memory array to specify the desired programming voltage delta increase for a given failing percentage of data bits further comprises profiling the Flash memory array by characterizing the non-volatile memory array manufacturing process.

32. A non-volatile memory device comprising:

a non-volatile memory array; and

a control circuit, wherein the control circuit is adapted to program a plurality of data bits into the non-volatile memory array in a programming operation by applying an initial programming voltage to a plurality of memory cells that are selected to be programmed with the plurality of data bits, and attempting to program any memory cells of the plurality of memory cells that failed to program correctly by,

verifying the plurality of data bits programmed into the plurality of memory cells of the non-volatile memory array,

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells,

disabling programming of one or more memory cells that correctly programmed,

applying the increased programming voltage to program one or more bits of the data that failed to program correctly, and

repeating for one or more iteration cycles.

33. The non-volatile memory device of claim 32, wherein the control circuit is adapted to repeat for one or more iteration cycles, until none of the plurality of data bits fail to verify or a maximum number of iterations is reached.

34. The non-volatile memory device of claim 32, wherein the control circuit is adapted to increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle further comprises limiting a total programming voltage level to a specified maximum programming voltage level.

35. The non-volatile memory device of claim 32, wherein the control circuit is adapted to increase the programming voltage according to a profile of the non-volatile memory array that specifies the desired programming voltage delta increase for a given failing percentage of data bits.

36. The non-volatile memory device of claim 32, wherein the non-volatile memory device is one of a NAND architecture Flash memory device, a NOR architecture Flash memory device, an EEPROM memory device, a Polymer Memory device, a Ferroelectric Random Access Memory (FeRAM) device, an Ovionics Unified Memory (OUM) device, and a Magnetoresistive Random Access Memory (MRAM), Molecular Memory device.

37. A Flash memory device comprising:

a Flash memory array;

a plurality of sense amplifiers;

an I/O buffer;

a memory interface; and

a control state machine coupled to the Flash memory array, the I/O buffer, the plurality of sense amplifiers, and the memory interface, wherein the control state machine is adapted to program a plurality of data bits into the Flash memory array in a programming operation received at the memory interface by applying an initial programming voltage to a plurality of floating gate memory cells that are selected to be programmed with the plurality of data bits, and attempting to program any memory cells of the plurality of memory cells that failed to program correctly by,

verifying the plurality of data bits programmed into the plurality of memory cells of the Flash memory array,

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells,

disabling programming of one or more memory cells that correctly programmed,

applying the increased programming voltage to program one or more bits of the data that failed to program correctly, and

repeating for one or more iteration cycles.

38. The Flash memory device of claim 37, wherein the control state machine is adapted to repeat for one or more iteration cycles, until none of the plurality of data bits fail to verify or a maximum number of iterations is reached.

39. The Flash memory device of claim 37, wherein the control state machine is adapted to increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the Flash memory array during the programming cycle further comprises limiting a total programming voltage level to a specified maximum programming voltage level.

40. The Flash memory device of claim 37, wherein the control state machine is adapted to increase the programming voltage according to a profile of the Flash memory array that specifies the desired programming voltage delta increase for a given failing percentage of data bits.

41. The Flash memory device of claim 37, wherein the Flash memory device is one of a NAND architecture Flash memory device and a NOR architecture Flash memory device.

42. A system comprising:

a host coupled to a non-volatile memory device, wherein the non-volatile memory device comprises,

a non-volatile memory array; and

a control state machine circuit, wherein the control state machine circuit is adapted to program a plurality of data bits into the non-volatile memory array in a programming operation by applying an initial programming voltage to a plurality of memory cells that are selected to be programmed with the plurality of data bits, and attempting to program any memory cells of the plurality of memory cells that failed to program correctly by,

verifying the plurality of data bits programmed into the plurality of memory cells of the non-volatile memory array,

increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells,

disabling programming of one or more memory cells that correctly programmed,

applying the increased programming voltage to program one or more bits of the data that failed to program correctly, and

repeating for one or more iteration cycles.

43. The system of claim 42, wherein the control state machine circuit is adapted to repeat for one or more iteration cycles, until none of the plurality of data bits fail to verify or a maximum number of iterations is reached.

44. The system of claim 42, wherein the control state machine circuit is adapted to increasing the programming voltage in a selected relation to the percentage of the plurality of data bits that failed to correctly program into the plurality of memory cells of the non-volatile memory array during the programming cycle further comprises limiting a total programming voltage level to a specified maximum programming voltage level.

45. The system of claim 42, wherein the control state machine circuit is adapted to increase the programming voltage according to a profile of the non-volatile memory array that specifies the desired programming voltage delta increase for a given failing percentage of data bits.

46. The system of claim 42, wherein the non-volatile memory device is one of a NAND architecture Flash memory device, a NOR architecture Flash memory device, an EEPROM memory device, a Polymer Memory device, a Ferroelectric Random Access Memory (FeRAM) device, an Ovionics Unified Memory (OUM) device, and a Magnetoresistive Random Access Memory (MRAM), Molecular Memory device.

47. The system of claim 42, wherein the host is one of a processor and a memory controller.