Semiconductor memory

• US 20060285413A1
• Filed: 08/24/2006
• Published: 12/21/2006
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Shinozaki, Naoharu, Kanda, Tatsuya, Sato, Takahiko, Funyu, Akihiro
• Granted Patent: US 7,471,585 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 29/50016 of retention

Abstract

A refresh signal is output in response to a refresh request generated at predetermined cycles, and a refresh operation is performed. The refresh operation ends when a conflict occurs between an access request and the refresh request. Consequently, an access operation corresponding to the access request can be started earlier with a reduction in access time. The access time can be reduced further by changing the end time of the refresh operation in accordance with the timing of supply of the access request. Since a test circuit for notifying the state of the refresh operation to exterior is formed, the operation margin of the refresh operation can be evaluated in a short time. As a result, it is possible to reduce the development period of the semiconductor memory.

Claims

1. A semiconductor device comprising:

a memory core to include a plurality of volatile memory cells;

a command control circuit that generates an access command to access the memory core in response to an access request supplied through a command terminal, the access command is a read command or a write command; and

a control circuit coupled to the memory core, controlling the memory core to execute a first refresh operation before the memory core is accessed, and to execute a second refresh operation after the memory core is accessed, a first period of the first refresh operation is shorter than a second period of the second refresh operation, wherein a first portion of the memory core to be executed the first refresh operation is the same as a second portion of the memory core to be executed the second refresh operation.

2. The semiconductor device according to claim 1, further comprising a address input circuit receiving an external address signal in a way of address non-multiplex.

3. The semiconductor device according to claim 1, wherein the control circuit controls the memory core to execute the first and second refresh operations without receiving a refresh command signal supplied from an external of the semiconductor device.

4. The semiconductor device according to claim 1, wherein the first refresh operation includes a first read stage, a first amplifying stage and a first precharging stage and the second refresh operation includes a second read stage, a second amplifying stage and a second precharging stage, wherein:

a period of the first read stage and a period of the second read stage is substantially identical;

a period of the first read precharging and a period of the second precharging stage is substantially identical; and

a period of the first amplifying stage is shorter than a period of the second amplifying stage.

5. The semiconductor device according to claim 1, wherein the control circuit includes a refresh timer generating a refresh request at predetermined cycles and refresh counter circuit generating a refresh address signal.

6. The semiconductor device according to claim 5, further comprising:

an address input circuit receiving an external address signal through an address terminal and generating an address signal corresponding to the external address signal; and

a switch circuit coupled to the refresh counter circuit and the address input circuit, selecting one of the refresh address signal and the address signal as an internal address signal.

7. The semiconductor device according to claim 1, wherein the memory core comprises:

a plurality of word lines connected to the memory cells; and

a row decoder circuit coupled to the memory cells, receiving the internal address signal and activating at least a word line of the plurality of word lines in order to refresh a first memory cell connected to the activated word line when the refresh address signal is selected as the internal address signal.

8. The semiconductor device according to claim 7, wherein the memory core further comprises:

a plurality of bit lines connected to the memory cells; and

a plurality of sense amplifiers connected to the bit lines, wherein

the first memory cell connected to the activated word line outputting data to at least a first bit line of the plurality of bit lines and a first sense amplifier of the plurality of sense amplifiers amplifying the data from the first bit line in order to refresh the first memory cell.

9. The semiconductor device according to claim 6, wherein the switching circuit selecting one of the refresh address signal and the address signal in response to a signal supplied from the control circuit.

10. The semiconductor device according to claim 1 or 9, wherein the control circuit includes a refresh control circuit generating one of a first refresh signal and a second refresh signal in response to the refresh request supplied from the refresh timer, wherein

the refresh control circuit generates the first refresh signal when the memory core executes the first refresh operation and generates the second refresh signal when the memory core executes the second refresh operation.

11. The semiconductor device according to claim 10, wherein the control circuit includes a core control circuit receiving the access command from the command control circuit and the first and second refresh signals from the refresh control circuit, the refresh control circuit generating a first timing signal when the memory core executes the first refresh operation, and generating a second timing signal when the memory core executes the second refresh operation,

12. The semiconductor device according to claim 11, wherein the core control circuit includes a first timing control circuit receiving at least the first refresh signal and generating the first timing signal and a second timing control circuit receiving at least the second refresh signal and generating the second timing signal.

13. The semiconductor device according to claim 12, wherein the first timing control circuit receiving the access command and generating the first timing signal when the memory core executes a read operation or a write operation.

14. The semiconductor device according to claim 12, wherein the core control circuit includes a access timing control circuit receiving the access command and generating an access timing signal when the memory core executes a read operation or a write operation.

15. The semiconductor device according to claim 10, wherein the refresh control circuit includes a first refresh generator circuit generating the first refresh signal at a first output terminal and a second refresh generator circuit generating the second refresh signal at a second output terminal that is different from the first terminal.

16. The semiconductor device according to claim 10, wherein the refresh control circuit includes a first refresh generator circuit generating the first refresh signal at an output terminal and a second refresh generator circuit generating the second refresh signal at the output terminal.

17. A mobile apparatus comprising:

a memory core including a plurality of volatile memory cells;

a command control circuit coupled to the memory core, outputting an access command to the memory core in order to access the memory core in response to an access request supplied through a command terminal, the access command is a read command or a write command; and

a control circuit coupled to the memory core, controlling the memory core to execute a first refresh operation before the memory core is accessed, and to execute a second refresh operation after the memory core is accessed, a first period of the first refresh operation is shorter than a second period of the second refresh operation, wherein a first portion of the memory core to be executed the first refresh operation is the same as a second portion of the memory core to be executed the second refresh operation.

18. A cellular phone comprising:

a memory core including a plurality of memory cells;

a command control circuit coupled to the memory core, outputting an access command to the memory core in order to access the memory core in response to an access request supplied through a command terminal, the access command is a read command or a write command; and

a control circuit coupled to the memory core, controlling the memory core to execute a first refresh operation before the memory core is accessed, and to execute a second refresh operation after the memory core is accessed, a first period of the first refresh operation is shorter than a second period of the second refresh operation, wherein a first portion of the memory core to be executed the first refresh operation is the same as a second portion of the memory core to be executed the second refresh operation.

19. A semiconductor device comprising:

a memory core including a plurality of volatile memory cells;

a command control circuit generating an access command for accessing the memory core in response to an access request supplied through a command terminal, the access command is a read command or a write command; and

a control circuit coupled to the memory core, controlling the memory core to execute a first refresh operation before the memory core is accessed, and to execute a second refresh operation after the memory core is accessed, wherein

the control circuit includes a first timing control circuit generating a first timing for starting the second refresh operation and a second timing control circuit generating a second timing for starting the first refresh operation.

20. The semiconductor device according to claim 19, further comprising:

a refresh control circuit generating one of a first refresh signal for the first refresh operation and a second refresh signal for the second refresh operation, the first refresh signal is inputted to the second timing control circuit and the second refresh signal is inputted to the first timing control circuit.

21. A semiconductor device comprising:

a memory core including a plurality of volatile memory cells;

a command control circuit generating an access command for accessing the memory core in response to an access request supplied through a command terminal, the access command is a read command or a write command; and

a control circuit coupled to the memory core, controlling the memory core to execute a first refresh operation before the memory core is accessed, and to execute a second refresh operation after the memory core is accessed, wherein

the control circuit includes a first timing control circuit generating a first timing for reading from the memory core or writing to the memory core starting the second refresh operation and a second timing control circuit generating a second timing for starting the second refresh operation and a third timing for starting the first refresh operation.