Fuse circuit and electronic circuit

• US 20060285414A1
• Filed: 02/16/2006
• Published: 12/21/2006
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Kimura, Hiroyuki
• Granted Patent: US 7,254,080 B2
• Time in Patent Office: Days
• US Class Current: 365/225.700
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

A fuse circuit and an electronic circuit for outputting a signal in accordance with the breakage of fuses even when the resistances of the broken fuses differ, reducing leak currents, and lowering power consumption. The fuse circuit includes a plurality of fuse lines, each including a fuse connected to a low-potential ground line and to a high-potential line via a MOS transistor and a constant current source. The fuse lines also each includes an inverter having an input terminal connected between the MOS transistor and constant current source. A reference circuit is connected in parallel to the fuse lines and includes a current source, a transistor, and a resistor connected in series. The transistor of the reference circuit has an input terminal connected to its control terminal and to the control terminal of each MOS transistor.

Claims

1. A fuse circuit including a plurality of fuse lines, each including a constant current source, a control transistor, and a fuse connected in series between a high-potential line and a low-potential line, wherein the fuse circuit outputs a signal for each fuse line in accordance with the potential at a connection node between the constant current source and the control transistor of each fuse line, the fuse circuit comprising:

a reference circuit for providing the control transistor of each fuse line with a reference bias.

2. The fuse circuit according to claim 1, wherein:

the reference circuit is configured by connecting a reference current source, a reference transistor, and a reference resistor in series between the high-potential line and the low-potential line; and

the reference circuit provides the control transistor of each fuse line with a bias of the reference transistor as the reference bias by commonly using a control terminal of the reference transistor and a control terminal of the control transistor of each fuse line.

3. The fuse circuit according to claim 2, wherein the reference circuit has a device input terminal connected to the control terminal of the reference transistor.

4. The fuse circuit according to claim 2, wherein the control transistor of each fuse line and the reference transistor comprise at least one of N-channel and P-channel metal oxide semiconductor transistors.

5. The fuse circuit according to claim 1, wherein the reference bias provided by the reference circuit is variable.

6. The fuse circuit according to claim 1, further comprising a logical circuit connected to the connection node between the constant current source and the control transistor of each fuse line.

7. The fuse circuit according to claim 6, wherein the logical circuit is an inverter, the inverter generating an output signal that is provided to a transistor for performing a switching operation of a trimming circuit.

8. (canceled)