Dynamic lane, voltage and frequency adjustment for serial interconnect

• US 20060285553A1
• Filed: 08/23/2006
• Published: 12/21/2006
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Animesh Mishra, Seh Kwa
• Original Assignee: Animesh Mishra, Seh Kwa
• Inventors: Kwa, Seh, Mishra, Animesh
• Granted Patent: US 7,426,598 B2
• Time in Patent Office: Days
• US Class Current: 370/468
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter'"'"'s lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter'"'"'s bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Claims

1. A method, comprising:

propagating electronic signals within circuitry comprising a transmitter to;

select a number of said transmitter'"'"'s lanes;

set a speed for each of said lanes, said number and speed determining said transmitter'"'"'s bandwidth; and

,

set a driver supply voltage for each of said lanes wherein, power consumed by said transmitter as a consequence of said selecting and both said settings is less than a power that would have been consumed by said transmitter had another available combination of lane number, lane speed and supply voltage been effected for said transmitter.

2. The method in claim 1 wherein said selecting and both said settings has the least power consumption for said particular bandwidth amongst all available combinations of number of lanes, lanes speed and supply voltage for said transmitter.

3. The method in claim 1 wherein said electronic signals are downstream from a register.

4. The method in claim 2 further comprising performing binary to one hot encoding downstream from said register to said select number of said transmitter'"'"'s lanes.

5. The method in claim 1 further comprising setting a phase lock loop output signal frequency to set said lane speed.

6. The method in claim 1 wherein said phase lock loop output signal frequency is a function of said supply voltage.

7. The method in claim 1 wherein said supply voltage is a function of said phase lock loop output signal frequency.