Semiconductor device, and design method, inspection method, and design program therefor

• US 20060288324A1
• Filed: 08/24/2006
• Published: 12/21/2006
• Est. Priority Date: 11/01/2002
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: Umc Japan
• Inventors: Isobe, Shinobu
• Granted Patent: US 7,924,042 B2
• Time in Patent Office: Days
• US Class Current: 324/762.10
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308

Abstract

A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Claims

1-2. -2. (canceled)

3. An inspection method of inspecting a multilayer semiconductor device which includes a plurality of circuit blocks formed on a semiconductor substrate, the method comprising the step of:

performing inspection via an electrode of a measurement terminal, wherein the measurement terminal is provided on a wiring line which extends from one of the circuit blocks, the electrode is formed in an uppermost layer of the semiconductor device, and the measurement terminal has a pad in each of the remaining layers of the semiconductor device, and the pads are electrically connected with each other via contact holes, each contact hole passing through each insulating film of the semiconductor device.

4. An inspection method as claimed in claim 3, wherein the step of performing inspection includes measuring at least one of voltage and logic state of the wiring line on which the measurement terminal is provided, by one of making a probe contact the electrode of the measurement terminal and irradiating the electrode with an electron beam.

6. A multilayer semiconductor device which includes a plurality of circuit blocks formed on a semiconductor substrate and is inspected using an inspection method in accordance with claim 3, the semiconductor device comprises:

measurement terminals, each provided on a wiring line which extends from one of the circuit blocks, wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device and a pad provided in each of the remaining layers of the semiconductor device, and the electrode and the pads are connected with each other via contact holes.

7. A multilayer semiconductor device as claimed in claim 6, wherein the positions of the electrode and the pads are substantially the same in plan view.

5. (canceled)