Two-sided surround access transistor for a 4.5F2 DRAM cell

• US 20060289919A1
• Filed: 06/24/2005
• Published: 12/28/2006
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 7,902,598 B2
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.

Claims

1. A memory device comprising;

a semiconductor substrate;

a plurality of charge storage devices associated with the semiconductor substrate;

a plurality of digit lines associated with the semiconductor substrate;

a plurality of gates electrically interposed between a charge storage device and a digit line wherein a gate, a charge storage device and a digit line define a memory cell, wherein the gates are formed so as to be recessed into the semiconductor substrate such that a first depletion region is formed within the semiconductor substrate and such that, when the gate is activated, a conductive path is formed about the perimeter of the recessed gate within the semiconductor substrate to thereby allow charge to flow between the charge storage device and the corresponding digit line;

a plurality of isolation structures formed so as to be recessed within the semiconductor substrate and so as to define a second depletion region within the semiconductor substrate.

2. The device of claim 1, wherein the plurality of isolation structures are biased so as to define the second depletion region.

3. The device of claim 2, wherein the plurality of isolation structures are grounded.

4. The device of claim 2, wherein the plurality of isolation structures are biased such that the second depletion region merges with the corresponding first depletion region such that the doping level of the semiconductor substrate can be reduced without increasing the leakage current between memory cells.

5. The device of claim 1, wherein each of the plurality of cells comprise a first and a second plurality of recessed gates and a first and a second charge storage device and wherein each of the plurality of cells include a common source/drain region that is common between the first and second gates and is electrically coupled to a single digit line.

6. The device of claim 5, further comprising a plurality of source/drain regions that are electrically coupled to the charge storage device.

7. The device of claim 1, wherein the substrate comprises a p-doped substrate and wherein the plurality of recessed gates comprise recessed access devices.

8. The device of claim 1, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each cell defines an active area and wherein the active area of each cell is oriented at an angle of 45 degrees with respect to the bit line and word line.

9. The device of claim 1, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each cell defines an active area and wherein the active area of each cell is oriented at an angle of 0 degrees with respect to the bit line.

10. The memory device of claim 1 wherein the isolation structure is biased so as not to electrically conduct.

11. The memory device of claim 10 wherein the isolation structure is biased such that the isolation structure is in the depletion mode.

12. The memory device of claim 10 wherein the isolation structure is biased such that the isolation structure is in the accumulation mode.

13. The memory device of claim 1 wherein the isolation structure comprises a grounded recessed gate.

14. A memory device comprising:

a substrate having a first surface;

a plurality of memory cells arranged in a pattern on the substrate, wherein the plurality of memory cells include a charge storage device and a recessed access device formed so as to extend into the substrate, wherein the recessed access device induces a depletion region in the substrate and further defines a current flow path about the recessed perimeter of the recessed access device within the substrate;

a plurality of isolation structures formed in the substrate, so as to isolate the plurality of memory cells from each other wherein the plurality of isolation structures comprised recessed access devices that are formed so as to extend into the substrate, wherein the plurality of isolation structures induce a second depletion region in the substrate.

15. The memory device of claim 14, wherein the plurality of memory cells include a charge storage device formed on the first surface of the substrate and a digit line wherein the recessed access device comprises a recessed access transistor having a gate formed so as to extend into the substrate.

16. The memory device of claim 15, wherein the recessed access transistor further includes a pair of source/drain regions formed adjacent the first surface of the substrate and wherein the recessed access transistor includes a gate structure that extends inward from the first surface into the substrate such that activation of the gate results in the formation of a conductive channel so that current flows between the two source/drain regions.

17. The device of claim 15, wherein the plurality of isolation structures comprise a plurality of gate structures that are formed so as to extend into the substrate from the first surface and wherein the plurality of gate structures are grounded.

18. The device of claim 17, wherein the second depletion region formed by the plurality of isolation structures merges with the corresponding first depletion region induced by the recessed access device of the cell such that the doping level of the semiconductor substrate can be reduced without increasing the leakage current between memory cells.

19. The device of claim 16, wherein each of the plurality of cells comprise a first and a second plurality of recessed gates and a first and a second charge storage device and wherein each of the plurality of cells include a common source/drain region that is common between the first and second gates and is electrically coupled to a single digit line.

20. The device of claim 19, further comprising a plurality of source/drain regions that are electrically coupled to the charge storage device.

21. The device of claim 14, wherein the substrate comprises a p-doped substrate and wherein the plurality of recessed gates comprise recessed access devices.

22. The device of claim 14, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each cell defines an active area and wherein the active area of each cell is oriented at an angle of 45 degrees with respect to the bit line and word line.

23. The device of claim 14, further comprising a word line that is used to activate the gate of a plurality of cells and wherein the bit line also electrically connects to a plurality of cells and wherein the gate of each cell defines an active area and wherein the active area of each cell is oriented at an angle of 0 degrees with respect to the bit line.

24. A memory device comprising:

a substrate having a first surface;

a first memory construction comprising;

a first memory storage device;

a first digit line; and

a first transistor construction having a first recessed gate that extends into the substrate from the first surface, a first source, and a first drain, wherein the first memory storage device is electrically coupled to the first source, and the first digit line is electrically coupled to the first drain;

a second memory construction comprising;

a second memory storage device;

a second digit line; and

a second transistor construction having a second recessed gate, a second source, and a second drain, wherein the second memory storage device is electrically coupled to the second source, and the second digit line is electrically coupled to the second drain;

wherein the first and second transistor constructions are recessed access devices; and

a grounded recessed transistor gate construction interposed between the first and second memory constructions.

25. The memory device of claim 24 wherein the depletion region of the grounded transistor gate construction merges with the depletion region of the first and second transistor constructions.

26. The memory device of claim 24 wherein the first and second transistor constructions are two-sided access transistors.

27. The memory device of claim 24 wherein the memory device is a 4.5F2 DRAM cell.

28. The memory device of claim 24 wherein the first digit line and the second digit line are the same.

29. A memory device comprising:

a substrate having a first surface;

a first memory construction comprising;

a first transistor construction having a first recessed gate that extends into the substrate from the first surface;

a first source; and

a first drain, the first recessed gate interposed between the first source and the first drain;

a second memory construction comprising;

a second transistor construction having a second recessed gate that extends into the substrate from the first surface;

a second source; and

a second drain, the second recessed gate interposed between the second source and the second drain; and

a recessed transistor gate construction interposed between the first and second memory constructions, wherein the recessed transistor gate construction is biased so as not to electrically conduct between the first and the second transistor constructions.

30. The device of claim 29, wherein the recessed transistor gate construction is biased such that the recessed transistor gate construction is in the depletion mode.

31. The device of claim 29, wherein the recessed transistor gate construction is biased such that the recessed transistor gate construction is in the accumulation mode.

32. The device of claim 29, wherein the recessed transistor gate construction is grounded.

33. The device of claim 29 further comprising a first memory storage device electrically coupled to the first source and a first digit line electrically coupled to the first drain.

34. The device of claim 29 further comprising a second memory storage device electrically coupled to the second source and a second digit line electrically coupled to the second drain.