×

Two-sided surround access transistor for a 4.5F2 DRAM cell

  • US 20060289919A1
  • Filed: 06/24/2005
  • Published: 12/28/2006
  • Est. Priority Date: 06/24/2005
  • Status: Active Grant
First Claim
Patent Images

1. A memory device comprising;

  • a semiconductor substrate;

    a plurality of charge storage devices associated with the semiconductor substrate;

    a plurality of digit lines associated with the semiconductor substrate;

    a plurality of gates electrically interposed between a charge storage device and a digit line wherein a gate, a charge storage device and a digit line define a memory cell, wherein the gates are formed so as to be recessed into the semiconductor substrate such that a first depletion region is formed within the semiconductor substrate and such that, when the gate is activated, a conductive path is formed about the perimeter of the recessed gate within the semiconductor substrate to thereby allow charge to flow between the charge storage device and the corresponding digit line;

    a plurality of isolation structures formed so as to be recessed within the semiconductor substrate and so as to define a second depletion region within the semiconductor substrate.

View all claims
  • 8 Assignments
Timeline View
Assignment View
    ×
    ×