COMPOSITE GATE STRUCTURE IN AN INTEGRATED CIRCUIT

• US 20060289920A1
• Filed: 06/22/2005
• Published: 12/28/2006
• Est. Priority Date: 06/22/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, I-Lu, Han, Liang-Kai, Chen, Kuang-Hsin
• Granted Patent: US 7,183,596 B2
• Time in Patent Office: Days
• US Class Current: 257/310
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

Claims

1. An integrated circuit comprising:

a substrate;

a first MOS device comprising;

a first high-k dielectric on the substrate; and

a first metal gate having a first work function over the first high-k dielectric;

a second MOS device comprising;

a second high-k dielectric on the substrate; and

a second metal gate having a second work function over the second high-k dielectric, the second work function being different from the first work function;

a third MOS device comprising;

a gate dielectric on the substrate; and

a patterned silicon layer directly on the first metal gate, the second metal gate and the gate dielectric.

2. The integrated circuit of claim 1 wherein:

the first MOS device is an NMOS device and the first work function is less than about 4.6 eV; and

the second MOS device is a pMOS device and the second work function is greater than about 4.8 eV.

3. The integrated circuit of claim 1 wherein the second metal gate comprises a first metal layer and an additional metal layer, the additional metal layer comprising a same material as the first metal gate.

5. The integrated circuit of claim 1 wherein the first and the second high-k dielectrics have a k value of greater than about 8.

6. The integrated circuit of claim 1 wherein the first high-k dielectric and the second high-k dielectric comprise same materials.

7. The integrated circuit of claim 1 wherein the silicon gate has a thickness of greater than about 500 Å

.

8. The integrated circuit of claim 1 wherein the first and second metal gates have thicknesses of between about 20 Å

and about 300 Å

.

9. The integrated circuit of claim 1 wherein the gate dielectric comprises high-k materials.

10. The integrated circuit of claim 8 wherein the substrate further comprises an interfacial layer underlying the gate dielectric.

12. The method of claim 10 wherein:

the first MOS device is an NMOS device and the first work function is less than about 4.6 eV; and

the second MOS device is a pMOS device and the second work function is greater than about 4.8 eV.

13. The method of claim 10 further comprising:

forming the second metal layer on the first metal layer; and

patterning the second metal layer to form a portion of the first gate stack.

14. The method of claim 10 further comprising:

forming the silicon layer over the first metal layer and the second metal layer; and

patterning the silicon layer to form respective portions of the first gate stack and the second gate stack.

15. The method of claim 10 further comprising doping at least one of the first metal layer and the second metal layer to adjust at least one of the first and the second work functions.

16. The method of claim 10 wherein the step of forming the gate dielectric layer over the substrate in the second region further comprises:

forming the gate dielectric layer in the first region and the second region; and

removing the gate dielectric layer from the first region.

17. The method of claim 10 further comprising removing the high-k dielectric layer from the second region using a chlorine-based solvent.

18. The method of claim 10 further comprising patterning the gate dielectric layer by ion bombardment and chemical reaction.

19. The method of claim 10 further comprising forming a masking layer after the forming the first metal layer.

20. The method of claim 10 further comprising doping the silicon layer to adjust a work function of the silicon layer.

4. (canceled)

11. A method of forming an integrated circuit, the method comprising:

providing a substrate having a first region and a second region, wherein the first region further comprises a third region and a fourth region;

forming a high-k dielectric layer on the substrate in the first region;

forming a first metal layer having a first work function over the high-k dielectric layer in the third region;

forming a second metal layer having a second work function over the high-k dielectric layer in the fourth region;

forming a gate dielectric layer over the substrate in the second region;

forming a silicon layer over the gate dielectric layer;

patterning the high-k dielectric layer and the first metal layer to form a first gate stack of a first MOS device;

patterning the high-k dielectric layer and the second metal layer to form a second gate stack of a second MOS device; and

patterning the gate dielectric layer and the silicon layer to form a third gate stack of a third MOS device.