Power amplifier utilizing quadrature hybrid for power dividing, combining and impedance matching

• US 20060290444A1
• Filed: 06/23/2005
• Published: 12/28/2006
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies Wireless IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: Chen, Pin-Fan
• Granted Patent: US 7,696,841 B2
• Time in Patent Office: Days
• US Class Current: 333/118
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/21103 An impedance adaptation circuit being added at the input of a power amplifier stage
• CPC Class Codes: H03F 2203/21112 A filter circuit being added at the input of a power amplifier stage
• CPC Class Codes: H03F 2203/21139 An impedance adaptation circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 2203/21157 A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

A balanced power amplifier that includes two or more power amplifiers with equal but phase-shifted signal paths. Balanced power amplifiers need to achieve phase delay and also need to perform power combining. A power amplifier includes at least one quadrature hybrid (also referred to as a branch-line coupler). The quadrature hybrid is utilized for multiple functions, such as power dividing, power combining, impedance matching or a combination thereof. This implementation with the quadrature hybrid reduces the amount of area needed to implement the balanced power amplifier.

Claims

1. A power amplifier comprising:

a quadrature hybrid and input impedance matching network;

at least one amplifier that includes an output electrode; and

a quadrature hybrid and an output impedance matching network.

2. The power amplifier of claim 1 further comprising:

bias circuitry that biases the amplifier.

3. The power amplifier of claim 1 wherein the quadrature hybrid and input impedance matching network includes

a first node;

a second node;

a first branch that includes a first electrode coupled to the first node and a second electrode coupled to the second node;

a third node;

a second branch that includes a first electrode coupled to the first node and a second electrode coupled to the third node;

a fourth node;

a third branch that includes a first electrode coupled to the third node and a second electrode coupled to the fourth node; and

a fourth branch that includes a first electrode coupled to the second node and a second electrode coupled to the fourth node.

4. The power amplifier of claim 1 wherein the quadrature hybrid and output impedance matching network includes

a first node;

a second node;

a first branch that includes a first electrode coupled to the first node and a second electrode coupled to the second node;

a third node;

a second branch that includes a first electrode coupled to the first node and a second electrode coupled to the third node;

a fourth node;

a third branch that includes a first electrode coupled to the third node and a second electrode coupled to the fourth node; and

a fourth branch that includes a first electrode coupled to the second node and a second electrode coupled to the fourth node.

5. The power amplifier of claim 1 wherein the quadrature hybrid and input impedance matching network is implemented with a plurality of lump elements.

6. The power amplifier of claim 1 wherein the quadrature hybrid and input impedance matching network exhibits a low pass frequency response.

7. The power amplifier of claim 1 wherein the quadrature hybrid and input impedance matching network exhibits a high pass frequency response.

8. The power amplifier of claim 1 wherein the quadrature hybrid and output impedance matching network is implemented with a plurality of lump elements.

9. The power amplifier of claim 1 wherein the quadrature hybrid and output impedance matching network exhibits a low pass frequency response.

10. The power amplifier of claim 1 wherein the quadrature hybrid and output impedance matching network exhibits a high pass frequency response.

12. The power amplifier of claim 1 wherein the power amplifier is implemented in a monolithic microwave integrated circuit (MMIC).

13. The power amplifier of claim 1 wherein the power amplifier is utilized in a code-division multiple access (CDMA) mobile handset.

14. The power amplifier of claim 1 wherein the power amplifier is utilized in a code-division multiple access (CDMA) mobile handset that employs one of Cellular mobile telephone frequencies and PCS mobile telephone frequencies.