Method and system for driving a light emitting device display

• US 20060290614A1
• Filed: 06/08/2006
• Published: 12/28/2006
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, G. Reza, Nathan, Arokia
• Granted Patent: US 7,852,298 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0216 Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element

Abstract

A method and system for driving a light emitting device display is provided. The system provides a timing schedule which increases accuracy in the display. The system may provide the timing schedule by which an operation cycle is implemented consecutively in a group of rows. The system may provide the timing schedule by which an aging factor is used for a plurality of frames.

Claims

1. A display system comprising:

a pixel array including a plurality of pixel circuits arranged in row and column, the pixel circuit having a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device, the pixel circuit including a path for programming, and a second path for generating the threshold of the drive transistor;

a first driver for providing data for the programming to the pixel array; and

a second driver for controlling the generation of the threshold of the drive transistor for one or more drive transistors, the first driver and the second driver driving the pixel array to implement the programming and generation operations independently.

2. A display system as claimed in claim 1, wherein the pixel circuits are divided into a plurality of segments, the first driver and the second driver driving the pixel array to implement the programming operation to a segment and the generation operation to another segment.

3. A display system as claimed in claim 2, wherein each segment includes a plurality of rows, the generation operation for each row in the segment is carried out consecutively.

4. A display system as claimed in claim 1, the pixel circuits are divided into a plurality of segments, each segment including a plurality of rows, the generation operation for each row in the segment being carried out consecutively.

5. A display system as claimed in claim 1, wherein the switch transistor includes a first switch transistor and a second switch transistor, the gate terminal of the first switch transistor being connected to a first select line, the gate terminal of the second switch transistor being connected to a second select line, the first and second select lines being driven by the second driver, the first terminal of the second switch transistor being connected to the gate terminal of the drive transistor, the first terminal of the first switch transistor being connected to a data line and the second terminal of the first switch transistor being connected to the gate of the drive transistor, the data line being driven by the first driver, the capacitor being connected to the gate of the drive transistor and the light emitting device.

6. A display system as claimed in claim 1, wherein the capacitor includes a first capacitor and a second capacitor, the switch transistor includes a first switch transistor, a second switch transistor and a third switch transistor, the gate terminal of the first and second switch transistors being connected to a first select line, the gate terminal of the third switch transistor being connected to a second select line, the first and second select lines being driven by the second driver, the first terminal of the third switch transistor being connected to a data line driven by the first driver and the second terminal of the third switch transistor being connected to the first and second capacitors, the first terminal of the second switch transistor being connected to the first and capacitors, the first terminal of the first switch transistor being connected to the drive transistor and the light emitting device and the second terminal of the first switch transistor being connected to the gate of the drive transistor, the first and second capacitors being connected to the gate of the drive transistor in series.

19. A display system as claimed in claim 1, wherein at least one of the transistors is fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductor including organic transistor, NMOS/PMOS technology or CMOS technology including MOSFET, a p-type material, or n-type material.

21. A pixel driver for a light emitting device, comprising:

a capacitor, a switch transistor and a driver transistor defined by claim 5.

22. A pixel driver for a light emitting device, comprising:

a capacitor, a switch transistor and a driver transistor defined by claim 6.

7. A method of driving a display system, the display system comprising a pixel array including a plurality of pixel circuits arranged in row and column, the pixel circuit having a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device, the pixel circuit including a path for programming, and a second path for generating the threshold of the drive transistor, the method comprising the steps of:

controlling the generation of the threshold of the drive transistor for one or more drive transistors,

providing data for the programming to the pixel array, independently from the step of controlling.

8. A method as claimed in claim 7, wherein the pixel circuits are divided into a plurality of segments, each segment including a plurality of rows, the step of controlling executes the generation operation for each row in the segment consecutively.

9. A display system comprising:

a pixel array including a plurality of pixel circuits arranged in row and column, the pixel circuit having a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device;

a first driver for providing data to the pixel array for programming; and

a second driver for generating and storing an aging factor of each pixel circuit in a row into the corresponding pixel circuit, and programming and driving the pixel circuit in the row for a plurality of frames based on the stored aging factor,

the pixel array being divided into a plurality of segments, at least one of signal lines driven by the second driver for generating the aging factor being shared in a segment.

10. A display system as claimed in claim 9, wherein the sequence of programming rows in the segment is changeable under the control of the first and second drivers.

11. A display system as claimed in claim 10, wherein a compensation interval is assigned to each segment for displaying, the compensation interval including a compensation cycle, a generation frame cycle for generating the aging factor, and a post compensation frames cycles for normal operation based on the aging factor generated in the generation frame cycle, the post compensation frames cycles having (L−

1) cycles where L represents the number of frames in the compensation interval.

12. A display system as claimed in claim 9, wherein the capacitor includes a first capacitor and a second capacitor, the switch transistor includes a first switch transistor, a second switch transistor and a third switch transistor, the gate terminal of the first and second switch transistors being connected to a first select line, the gate terminal of the third switch transistor being connected to a second select line, the first and second select lines being driven by the second driver, the first terminal of the third switch transistor being connected to a data line driven by the first driver and the second terminal of the third switch transistor being connected to the first and second capacitors, the first terminal of the second switch transistor being connected to the first and second capacitors and the second terminal of the second switch transistor being connected to a controllable voltage line driven by the second driver, the first terminal of the first switch transistor being connected to the first terminal of the drive transistor and the light emitting device and the second terminal of the first switch transistor being connected to the gate of the drive transistor, the first and second capacitors being connected to the gate of the drive transistor and the controllable voltage line in series, the second terminal of the drive transistor being connected to the controllable voltage line, at least one of the select lines and the controllable voltage line being shared by the segment.

13. A display system as claimed in claim 9, wherein the capacitor includes a first capacitor and a second capacitor, the switch transistor includes a first switch transistor and a second switch transistor, the gate terminal of the first switch transistor being connected to a first select line, the gate terminal of the second switch transistor being connected to a second select line, the first and second select lines being driven by the second driver, the first terminal of the second switch transistor being connected to a data line driven by the first driver and the second terminal of the second switch transistor being connected to the first and second capacitors, the first terminal of the first switch transistor being connected to the first terminal of the drive transistor and the light emitting device and the second terminal of the first switch transistor being connected to the gate of the drive transistor, the first and second capacitors being connected to the gate of the drive transistor and a controllable voltage line driven by the second driver in series, the second terminal of the drive transistor being connected to the controllable voltage line, at least one of the select lines and the controllable voltage line being shared by the segment.

14. A display system as claimed in claim 9, wherein the capacitor includes a first capacitor and a second capacitor, the switch transistor includes a first switch transistor, a second switch transistor and a third switch transistor, the gate terminal of the first switch transistor being connected to a signal line, the gate terminal of the second switch transistor being connected to a first select line, the gate terminal of the third switch transistor being connected to a second select line, the first and second select lines and the signal line being driven by the second driver, the first terminal of the first transistor being connected to the first capacitor and the second terminal of the first switch transistor being connected to the first terminal of the drive transistor, the first terminal of the second switch transistor being connected to a data line driven by the first driver and the second terminal of the second switch transistor being connected to the first and second capacitors, the first terminal of the third switch transistor being connected to the first terminal of the drive transistor, the first and second capacitors being connected to the gate of the drive transistor in series, at least one of the select lines and the signal line being shared by the segment.

15. A display system as claimed in claim 13, wherein the voltage line is controllable by the second driver, the second select line being the controllable voltage line, at least one of the signal line and the controllable voltage line being shared by the segment.

20. A display system as claimed in claim 9, wherein at least one of the transistors is fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductor including organic transistor, NMOS/PMOS technology or CMOS technology including MOSFET, a p-type material or n-type material.

23. A pixel driver for a light emitting device, comprising:

a capacitor, a switch transistor and a driver transistor defined by claim 12.

24. A pixel driver for a light emitting device, comprising:

a capacitor, a switch transistor and a driver transistor defined by claim 13.

25. A pixel driver for a light emitting device, comprising:

a capacitor, a switch transistor and a driver transistor defined by claim 14.

26. A pixel driver for a light emitting device, comprising:

a capacitor, a switch transistor and a driver transistor defined by claim 15.

16. A method of driving a display system comprising a pixel array including a plurality of pixel circuits arranged in row and column, the pixel circuit having a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device, the pixel array being divided into a plurality of segments, the method comprising the steps of:

generating an aging factor of each pixel circuit using a segment signal and storing the aging factor into the corresponding pixel circuit for each row, the segment signal being shared by each segment; and

programming and driving the pixel circuit in the row for a plurality of frames based on the stored aging factor.

17. A method as claimed in claim 16, further comprising the step of changing the sequence of programming rows in the segment.

18. A method as claimed in claim 17, wherein a compensation interval is assigned to each segment for displaying, the compensation interval including a compensation cycle, a generation frame cycle for generating the aging factor, and a post compensation frames cycles for normal operation using the aging factor generated in the generation frame cycle, the post compensation frames cycles having (L−

1) cycles where L represents the number of frames in the compensation interval.