Drive circuit

• US 20060290718A1
• Filed: 06/22/2006
• Published: 12/28/2006
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ishida, Tatsuya
• Granted Patent: US 8,077,189 B2
• Time in Patent Office: Days
• US Class Current: 345/691
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2330/028 Generation of voltages supplied to electrode drivers in a matrix display other than LCD
• CPC Class Codes: G09G 3/2081 with combination of amplitude modulation and time modulation space and time error diffusion G09G3/2066
• CPC Class Codes: G09G 3/22 using controlled light sources

Abstract

A drive circuit of the present invention is a drive circuit for driving a display element in accordance with grayscale information, which circuit outputs a drive waveform controlled through (i) plural-stepped voltage amplitude modulation and (ii) a pulse width modulation which is settable for each voltage amplitude of the plural-stepped voltage amplitude modulation, the drive circuit including an output control section for (A) latching a pulse width corresponding to a maximum voltage amplitude, according to the grayscale information, which amplitude is one of plural steps of amplitudes of the drive waveform, and which amplitude is to be outputted, so as to control a pulse width of the maximum voltage amplitude, and (B) outputting a maximum pulse width for a voltage amplitude smaller than the maximum voltage amplitude. With this drive circuit, it is possible to realize a drive circuit, whose circuit scale is smaller, for driving a display device including luminescent elements arranged in a matrix manner, the drive circuit generating a drive signal having been controlled by a voltage amplitude modulation (AM) and a pulse width modulation (PWM)

Claims

1. A drive circuit for outputting a drive waveform so as to drive a display element in accordance with grayscale information, the drive waveform being controlled by (i) a plural-stepped voltage amplitude modulation and (ii) a pulse width modulation which is settable for each voltage amplitude of the plural-stepped voltage amplitude modulation,

said drive circuit comprising output control means for controlling the drive waveform,

at a time of modulating arbitrary grayscale information, said output control means (A) latching a signal indicating a pulse width corresponding to a maximum voltage amplitude to be outputted so as to control a pulse width of the maximum voltage amplitude, and (B) outputting a maximum pulse width for a voltage amplitude smaller than the maximum voltage amplitude.

2. A drive circuit for outputting a drive waveform so as to drive a display element in accordance with grayscale information, the drive waveform being controlled by (i) a plural-stepped voltage amplitude modulation and (ii) a pulse width modulation which is settable for each voltage amplitude of the plural-stepped voltage amplitude modulation, said drive circuit comprising:

voltage value data latching means, at a time of modulating arbitrary grayscale information, for latching first data indicating a maximum voltage amplitude to be outputted;

PWM data latching means, at the time of modulating arbitrary grayscale information, for latching second data indicating a pulse width of the maximum voltage amplitude;

output-range signal generating means, at the time of modulating arbitrary grayscale information, for generating and outputting an output-range signal in accordance with a maximum pulse width of each voltage amplitude; and

one or more control means, at the time of modulating arbitrary grayscale information, for

(a) outputting a pulse width of the maximum voltage amplitude according to the first data and the second data, and (b) outputting a maximum pulse width according to the output-range signal, when a voltage amplitude is smaller than the maximum voltage amplitude.

3. The drive circuit as set forth in claim 2, wherein:

(A) the drive waveform is a drive waveform (i) which has been subjected to the voltage amplitude modulation in which n-step electric potentials sequentially increase from V1 to Vn (where n is an integer of not less than

     1) in accordance with the number of grayscale units indicated by the grayscale information and (ii) which has been subjected to the pulse width modulation in which, for each of the n-step voltage amplitudes, m-step pulse widths fall within a range of a unit pulse width Δ

T to a maximum pulse width Δ

T×

m (where m is an integer of not less than

     1) in accordance with the number of grayscale units indicated by the grayscale information;

(B) when expressing an outline shape of the drive waveform by placing in a matrix grayscale blocks, having a size of (Δ

Vk×

Δ

T), whose number corresponds to that of the grayscale units, the matrix being formed in a plane defined by an axis of coordinate including (i) a voltage axis extending longitudinally on which axis a voltage increases as the voltage is located upward and (ii) a time axis extending transversely on which a time increases as the time is located rightward, the matrix including n rows of first row to n-th row for each Δ

Vk=Vk−

V(k−

1) (where k is an integer and is 1≦

k≦

n, V0 is a reference electric potential corresponding to zero brightness, and Δ

Vk indicates one grayscale unit expressed as a voltage amplitude) and m columns of first column to m-th column for each Δ

T indicating one grayscale unit expressed as a pulse width;

(C) the shape of the drive waveform is formed by sequentially placing the grayscale blocks from a lowermost row, according to rules such that;

(i) the grayscale blocks are placed, with no space between the grayscale blocks, in a placeable range which is determined for each row, and (ii) when the placeable range of a lower row is filled with the grayscale blocks, the grayscale blocks are placed in a row above said lower row, and (D) said voltage value data latching means latches the first data indicating a row in which a final grayscale block is placed, in the drive waveform corresponding to the arbitrary grayscale information; and

(E) said PWM data latching means latches the second data indicating a column in which the final grayscale block is placed.

4. The drive circuit as set forth in claim 2, wherein

said output-range signal generating means commonly supplies the output-range signal to a plurality of said control means which respectively generate drive waveforms to be supplied to a plurality of pixels on a scanning line of a display element.

5. The drive circuit as set forth in claim 4, wherein:

the output-range signal is generated based on;

(A) output-starting position data and output-ending position data, stored in an output-range data memory; and

(B) a digital signal of at least two bits causing counting up or counting down.

6. The drive circuit as set forth in claim 4, wherein:

said output-range signal generating means simultaneously generates, as the output-range signal;

(A) a first output-range signal generated based on (i) output-starting position data and output-ending position data, stored in an output-range data memory, and (ii) a digital signal of at least two bits causing counting up; and

(B) a second output-range signal based on (i) the output-starting position data and the output-ending position data, and (ii) a digital signal of at least two bits causing counting down.