Liquid crystal display and thin film transistor array panel therefor

• US 20060290829A1
• Filed: 03/27/2004
• Published: 12/28/2006
• Est. Priority Date: 03/28/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Application Number:
  US10/550,899
• Publication Number:
  US 20060290829A1
• Time in Patent Office: Days
• US Class Current: 349/44
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate

Abstract

A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer and a semiconductor layer sequentially on a substrate; a data line formed on the gate insulating layer and including a source electrode; a drain electrode formed at least in part on the semiconductor layer; a color filter formed on the data line and the drain electrode and having a first opening exposing the drain electrode at least in part; a light blocking layer formed on the color filter; a passivation layer formed on the color filter and the light blocking layer and having a contact hole exposing the drain electrode through the first opening of the color filter; a pixel electrode formed on the passivation layer and contacting the drain electrode through the contact hole; and a spacer formed on the passivation layer and disposed opposite the light blocking layer.

Claims

1. A thin film transistor array panel comprising:

a gate line formed on an insulating substrate including a gate electrode;

a gate insulating layer on the gate line;

a semiconductor layer on the gate insulating layer;

a data line formed on the gate insulating layer and including a source electrode;

a drain electrode formed at least in part on the semiconductor layer;

a color filter formed on the data line and the drain electrode and having a first opening exposing the drain electrode at least in part;

a light blocking layer formed on the color filter;

a passivation layer formed on the color filter and the light blocking layer and having a contact hole exposing the drain electrode through the first opening of the color filter;

a pixel electrode formed on the passivation layer and contacting the drain electrode through the contact hole; and

a spacer formed on the passivation layer and disposed opposite the light blocking layer.

2. The thin film transistor array panel of claim 1, wherein the light blocking layer comprises organic material including black pigment.

3. The thin film transistor array panel of claim 1, wherein the spacer comprises organic material.

4. The thin film transistor array panel of claim 1, further comprising a storage conductor firmed on the gate insulating layer, overlapping the gate line, and electrically connected to the pixel electrode.

5. The thin film transistor array panel of claim 4, wherein the color filter has a second opening exposing the storage conductor at least in part and the passivation layer further has a second contact hole exposing the storage conductor at least in part through the second opening for connection between the storage conductor and the pixel electrode.

6. The thin film transistor array panel of claim 1, further comprising a storage electrode formed under the gate insulating layer and overlapping the pixel electrode.

7. The thin film transistor array panel of claim 6, further comprising a storage conductor firmed on the gate insulating layer, overlapping the storage electrode, and electrically connected to the pixel electrode.

8. The thin film transistor array panel of claim 7, wherein the color filter has a second opening exposing the storage conductor at least in part and the passivation layer further has a second contact hole exposing the storage conductor at least in part through the second opening for connection between the storage conductor and the pixel electrode.

9. The thin film transistor array panel of claim 1, wherein the passivation layer comprises acrylic material or a chemical vapor deposition film having a dielectric constant smaller than 4.0.

10. The thin film transistor array panel of claim 1, wherein the semiconductor layer has substantially the same planar shape as the data lines and the drain electrodes except for a portion between the source electrode and the drain electrode.

11. A liquid crystal display comprising:

a first panel including a gate line, a data line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a light blocking layer including organic material and black pigment;

a second panel facing the first panel and including a common electrode; and

a spacer disposed between the first panel and the second panel to form a gap therebetween and overlapping the light blocking layer.

12. The liquid crystal display of claim 11, further comprising a color filter formed on the first panel and having an opening exposing the drain electrode at least in part.

13. The liquid crystal display of claim 11, further comprising a protrusion formed on at least one of the first and the second panels, having a height smaller than the spacer, and having a slanted lateral surface.