Liquid crystal display and fabricating method thereof

• US 20060290867A1
• Filed: 06/21/2006
• Published: 12/28/2006
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Nam, Seung Hee, Kwon, Oh Nam, Chang, Youn Gyoung, Ahn, Byung Chul, Yoo, Soon Sung, Cho, Heung Lyul
• Granted Patent: US 7,751,021 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes

Abstract

A liquid crystal display device and a fabricating method thereof for simplifying a process are disclosed. In the method of fabricating the liquid crystal display device, a first conductive pattern group including a gate line and a gate electrode, a common line and a common electrode, a pixel electrode and a pad is formed on a substrate. An insulating film including a plurality of contact holes and a semiconductor pattern is formed on the first mask pattern group. And a second conductive pattern group including a data line, a source electrode and a drain electrode is formed on an insulating film provided with the semiconductor pattern, and exposes an active layer of the semiconductor pattern

Claims

1. A liquid crystal display device, comprising:

a data line crossing a gate line on a substrate to define a pixel area;

an insulating film between the gate line and the data line;

a thin film transistor having a gate electrode, a drain electrode, and a source electrode, and connected to the gate line and the data line;

a plurality of pixel electrodes connected to the thin film transistor in the pixel area;

a plurality of common electrodes substantially parallel to the pixel electrodes in the pixel area;

a common line connected to the common electrodes; and

a pad connected to at least one of the gate line, the data line and the common line;

wherein the gate line, the gate electrode, the pixel electrodes, the common electrodes, the common line, and the pad include a transparent conductive layer.

2. The device of claim 1, wherein the gate line, the gate electrode and the common line have a multiple-layer structure including the transparent conductive layer and a substantially opaque conductive layer.

3. The device of claim 1, wherein at least a first of the common electrodes has a multiple-layer structure having the transparent conductive layer and a substantially opaque conductive layer, and at least a second of the common electrodes includes the transparent conductive layer.

4. The device of claim 1, wherein an outermost one of the common electrodes in the pixel area has a multiple layer structure having the transparent conductive layer and a substantially opaque conductive layer.

5. The device of claim 1, wherein the gate line, the gate electrode, the common line, at multiple-layer structure including the transparent conductive layer and a substantially opaque conductive layer.

6. The device of claim 5, wherein the transparent conductive layer extends beyond an edge of the substantially opaque conductive layer.

7. The device of claim 6, wherein the transparent conductive layer of the pad is exposed through a contact hole passing through the substantially opaque conductive layer.

8. The device of claim 1, further comprising:

a storage capacitor provided such that a pixel connecting line extending from the drain electrode of the thin film transistor overlaps with a portion of the common line with the insulating film therebetween.

9. The device of claim 8, further comprising:

a storage capacitor provided such that an upper storage electrode connected to at least one of the pixel electrodes overlaps with a portion of the gate line with the insulating film therebetween.

10. The device of claim 9, wherein the drain electrode and the upper storage electrode are connected to the at least one pixel electrode via a contact hole passing through the insulating film.

11. The device of claim 1, further comprising:

a storage capacitor provided such that an upper storage electrode connected to at least one of the pixel electrodes overlaps with a portion of the gate line with the insulating film therebetween.

12. The device of claim 11, wherein the drain electrode and the upper storage electrode are connected to the at least one pixel electrode via a contact hole passing through the insulating film.

13. The device of claim 1, wherein a surface of a channel exposed between the source electrode and the drain electrode of the thin film transistor is oxidized.

14. The device of claim 1, wherein the thin film transistor and the data line are covered by an alignment film.

15. The device of claim 5, further comprising:

a second insulating film on the multiple-layer structure including the transparent conductive layer of the gate line, the gate electrode, the at least one pixel electrode, the at least one common electrode, the common line and the pad.

16. The device of claim 1, wherein the data line is connected to the pad via a contact hole passing through the insulating film.

17. A method of fabricating a liquid crystal display device, comprising:

forming a first conductive pattern group including a gate line and a gate electrode, a common line, a plurality of common electrodes, a plurality of pixel electrodes and a pad on a substrate;

forming an insulating film including a plurality of contact holes and a semiconductor pattern on the first mask pattern group; and

forming a second conductive pattern group including a data line, a source electrode and a drain electrode on the insulating film and exposing an active layer of the semiconductor pattern.

18. The method of claim 17, wherein the gate line, the gate electrode and the common line have a multiple-layer structure including a transparent conductive layer and a substantially opaque conductive layer.

19. The method of claim 17, wherein at least a first of the common electrodes has a multiple-layer structure having a transparent conductive layer and a substantially opaque conductive layer, and at least a second of the common electrodes is formed of the transparent conductive layer.

20. The method of claim 17, wherein the pixel electrodes and the pad are formed of a transparent conductive layer.

21. The method of claim 17, wherein forming the first conductive pattern group includes:

forming a transparent conductive layer and a substantially opaque conductive layer on the substrate;

patterning the transparent conducive layer and the substantially opaque conductive layer; and

removing a portion of the substantially opaque conductive layer to expose the transparent conductive layer.

22. The method of claim 21, wherein the first conductive pattern group is formed by using one of a half tone mask and a diffractive exposure mask.

23. The method of claim 17, wherein the gate line, the gate electrode, the common line, at least one of the common electrodes, at least one of the pixel electrodes and the pad have a multiple-layer structure including a transparent conductive layer and a substantially opaque conductive layer.

24. The method of claim 23, wherein the transparent conductive layer is exposed along an edge of the substantially opaque conductive layer.

25. The method of claim 24, wherein forming the first conductive pattern group includes:

forming the transparent conductive layer and the substantially opaque conductive layer on the substrate;

forming a photo-resist pattern on the substantially opaque conductive layer;

patterning the transparent conductive layer and the substantially opaque conductive layer using the photo-resist pattern as a mask;

ashing the photo-resist pattern; and

etching the substantially opaque conductive layer exposed through the ashed photo-resist pattern.

26. The method of claim 23, wherein the transparent conductive layer of the pad is exposed via a contact hole passing through the substantially opaque conductive layer.

27. The method of claim 17, wherein forming the insulating film and the semiconductor pattern include:

forming an insulating film and a semiconductor layer on the substrate;

forming the plurality of contact holes passing through the insulting film; and

forming the semiconductor pattern by patterning the semiconductor layer.

28. The method of claim 27, wherein the plurality of contact holes and the semiconductor pattern are formed using one of a half tone mask and a diffractive exposure mask.

29. The method of claim 17, further comprising forming a storage capacitor by overlapping a pixel connecting line extending from the drain electrode with a portion of the common line with the insulating film therebetween.

30. The method of claim 29, further comprising forming an upper storage electrode connected to at least one of the pixel electrodes, and overlapped with a portion of the gate line with the insulating film therebetween along, wherein the upper storage electrode is formed with the second conductive pattern group.

31. The method of claim 30, wherein the pixel connecting line is connected to the pixel electrodes via a contact hole passing through the insulating film.

32. The method of claim 30, wherein the upper storage electrode are connected to the at least one pixel electrode via a contact hole passing through the insulating film.

33. The method of claim 17, further comprising forming an upper storage electrode connected to at least one of the pixel electrodes, and overlapped with a portion of the gate line with the insulating film therebetween along, wherein the upper storage electrode is formed with the second conductive pattern group.

34. The method of claim 33, wherein the pixel connecting line is connected to the pixel electrodes via a contact hole passing through the insulating film.

35. The method of claim 33, wherein the upper storage electrode are connected to the at least one pixel electrode via a contact hole passing through the insulating film.

36. The method of claim 17, further comprising oxidizing a surface of an active layer exposed between a source and a drain electrodes of the thin film transistor by a plasma surface process.

37. The method of claim 36, wherein the plasma surface process is performed on the condition that a photo-resist pattern remains for forming the second conductive pattern group.

38. The method of claim 17, further comprising forming an alignment film for covering the second conductive pattern group.

39. The method of claim 23, wherein forming the first conductive pattern group further includes:

forming a second insulating film on the multiple-layer structure of the gate line, the gate electrode, the at least one pixel electrode, the at least one common electrode, the common line and the pad.

40. The method of claim 17, wherein the data line is connected to the pad via a contact hole passing through the insulating film.

41. The method of claim 26, wherein the substantially opaque conductive layer of the pad exposed through the contact hole is removed upon forming of the second conductive pattern group.

42. The method of claim 17, wherein the gate and the data line define a pixel area and an outermost one of the common electrodes in the pixel area has a multiple layer structure having a transparent conductive layer and a substantially opaque conductive layer.