Flash memory cell and methods for programming and erasing

• US 20060291282A1
• Filed: 08/29/2006
• Published: 12/28/2006
• Est. Priority Date: 05/07/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: He, Yi, Liu, Zhizheng, Randolph, Mark, Liu, Zengtao
• Granted Patent: US 7,215,577 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors

Abstract

Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

Claims

1. A flash memory cell, comprising:

a source formed in a substrate;

a drain formed in the substrate, the source and the drain being spaced from one another on laterally opposite sides of a channel region of the substrate;

a dielectric material formed above the channel region of the substrate;

a charge trapping material formed over the dielectric material; and

a control gate formed over the charge trapping material, wherein the control gate is located directly on the charge trapping material and the electrons are directed from the control gate directly into the charge trapping material without traveling through an intermediary layer.

2. The flash memory cell of claim 1, wherein the dielectric material comprises an oxide.

3. The flash memory cell of claim 1, wherein the charge trapping material comprises silicon nitride.

4. The flash memory device of claim 1, wherein the control gate comprises polysilicon.

5. A gate structure for a flash memory cell, the gate structure comprising:

a dielectric material formed above a channel region of a substrate;

a charge trapping material formed over the dielectric material; and

a control gate formed over the charge trapping material, wherein the control gate is located directly on the charge trapping material and the electrons are directed from the control gate directly into the charge trapping material without traveling through an intermediary layer.

6. The gate structure of claim 5, wherein the dielectric material comprises an oxide.

7. The gate structure of claim 5, wherein the charge trapping material comprises silicon nitride.

8. The gate structure of claim 5, wherein the control gate comprises polysilicon.

9. A memory device comprising:

a core region of the device comprising a plurality of flash memory cells respectively comprising;

a source formed in a substrate;

a drain formed in the substrate, the source and the drain being spaced from one another on laterally opposite sides of a channel region of the substrate;

a dielectric material formed above the channel region of the substrate;

a charge trapping material formed over the dielectric material; and

a control gate formed over the charge trapping material, wherein the control gate is located directly on the charge trapping material and the electrons are directed from the control gate directly into the charge trapping material without traveling through an intermediary layer; and

a peripheral region of the device comprising I/O circuitry and programming circuitry.

10. The device of claim 9, wherein the programming circuitry is formed in the substrate and comprises x-direction decoders and y-direction decoders.

11. The device of claim 10, wherein the programming circuitry and the I/O circuitry operate to couple selected cells of the flash memory cells with selected voltages and/or impedances during program, erase, and read operations.

12. The device of claim 9, wherein the flash memory cells are arranged in a virtual ground configuration.

13. The device of claim 9, wherein the flash memory cells are arranged in a NOR configuration.

14. The device of claim 9, wherein the charge trapping material comprises silicon nitride.

15. The device of claim 9, wherein the control gate comprises polysilicon.

16. The device of claim 9, wherein rows of the flash memory cells have control gates coupled to corresponding wordlines and columns of the flash memory cells have drains coupled to corresponding bitlines and sources of adjacent flash memory cells.

17. A communication device comprising:

communication circuitry;

a flash memory device comprising;

flash memory cells respectively comprising;

a source formed in a substrate;

a drain formed in the substrate, the source and the drain being spaced from one another on laterally opposite sides of a channel region of the substrate;

a dielectric material formed above the channel region of the substrate;

a charge trapping material formed over the dielectric material; and

a control gate formed over the charge trapping material, wherein the control gate is located directly on the charge trapping material and the electrons are directed from the control gate directly into the charge trapping material without traveling through an intermediary layer;

programming circuitry; and

I/O circuitry coupled to the communication circuitry.

18. The device of claim 17, wherein the programming circuitry comprises x-direction decoders and y-direction decoders

19. The device of claim 17, wherein the I/O circuitry operates to couple selected cells of the flash memory cells with selected voltages and/or impedances during program, erase, and read operations.

20. The device of claim 17, wherein the flash memory cells maintain information from the communication circuitry.