System and method for programming cells in non-volatile integrated memory devices

• US 20060291285A1
• Filed: 08/02/2005
• Published: 12/28/2006
• Est. Priority Date: 02/06/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Guterman, Daniel C.
• Granted Patent: US 7,630,237 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.

Claims

1. A method of programming a multi-state storage element from an initial condition to one of a plurality of data states, comprising:

selecting a target state from the plurality of states; and

biasing the storage element, wherein the current between a first terminal and a second terminal of the storage element is limited to not exceed a value that is dependent upon the selected target state.

2. The method of claim 1, wherein the storage element belongs to a non-volatile memory comprised of an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows connected to word lines, the method further comprising:

selecting said storage element to program from said array, and

wherein said biasing the storage element comprises limiting the current on a bit line to which said storage element is connected to said value dependent upon the selected target state.

3. The method of claim 1, wherein said biasing the storage element includes applying a voltage difference between the first terminal and second terminal dependent upon the selected target state.

4. The method of claim 3, wherein the storage element belongs to a non-volatile memory comprised of an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows connected to word lines, the method further comprising:

selecting said storage element to program from said array, and

wherein said biasing the storage element comprises limiting the current on a bit line to which said storage element is connected to said value dependent upon the selected target state and said voltage difference is determined by setting a voltage level dependent upon the selected target state on the bit line to which said storage element is connected.

5. The method of claim 1, wherein said first and second terminals are the source and drain of the storage element and said biasing the storage element includes applying a programming waveform to the control gate of the storage element.

6. The method of claim 5, wherein said programming waveform is a series of pulses.

7. The method of claim 1, wherein the storage element is a charge-storing device.

8. The method of claim 7, wherein the storage element is a floating gate transistor and said first and second terminals are the source and drain of the storage element.

9. A non-volatile memory comprising:

an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows connected to word lines;

programming circuitry connectable to the bit lines and the word lines to apply a set of voltages to program a selected storage element to a target one of said multi-states during a programming process; and

current limiting circuitry connectable to said bit lines to limit the current through the selected element to not exceed a value dependent upon the selected target state during the programming process.

10. The non-volatile memory of claim 9, wherein said set of voltages includes applying a source-drain voltage difference dependent upon the selected target state.

11. The non-volatile memory of claim 9, wherein said set of voltages includes applying a programming waveform to the control gate of the storage element.

12. The non-volatile memory of claim 11, wherein said programming waveform is a series of pulses.

13. The non-volatile memory of claim 9, wherein the storage element is a charge-storing device.

14. The non-volatile memory of claim 13, wherein the storage element is a floating gate transistor.

15. In a non-volatile memory including an array of multi-state storage elements connected in a plurality of columns along bit lines and along one or more rows each connected to a corresponding word line, a method of concurrently programming a plurality of the storage elements connected along a common word line from an initial condition to one of a plurality of data states, comprising:

providing for each of said plurality of the storage elements connected along the common word line a corresponding target state from said plurality of data states; and

biasing said plurality of the storage elements, wherein the biasing includes;

limiting the current on each of the respective bit lines to which said plurality of the storage elements is connected to not exceed a value that is dependent upon the corresponding target state of the respective storage element; and

applying a programming waveform to the common word line.

16. The method of claim 15, wherein said current on each of the respective bit lines is the source-drain current of the corresponding storage elements and the common word line supplies the programming waveform to the control gates of each of said plurality of the storage elements.

17. The method of claim 16, wherein said programming waveform is a series of pulses.

18. The method of claim 15, wherein the storage elements are charge-storing devices.

19. The method of claim 18, wherein the storage elements are floating gate transistors.

20. A non-volatile memory comprising:

an array of multi-state storage elements connected in one or more columns along bit lines and along one or more rows each connected to a corresponding word line;

programming circuitry connectable to the bit lines and the word lines to apply a set of voltages to concurrently program a plurality of the storage elements connected along a common word line from an initial condition to a corresponding target state from one of a plurality of data states; and

current limiting circuitry connectable to said bit lines to individually limit the current through said plurality of the storage elements to not exceed a value that is dependent upon the corresponding target state of the respective storage elements.

21. The non-volatile memory of claim 20, wherein said set of voltages includes applying a programming waveform to common word line.

22. The non-volatile memory of claim 21, wherein said programming waveform is a series of pulses.

23. The non-volatile memory of claim 20, wherein the storage elements are charge-storing devices.

24. The non-volatile memory of claim 23, wherein the storage elements are floating gate transistors.