NON-VOLATILE MEMORY DEVICE HAVING PAGE BUFFER FOR VERIFYING PRE-ERASE
First Claim
1. A non-volatile memory device, comprising:
- a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines; and
a plurality of page buffers connected to the bit lines through a sensing line, each of the plurality of page buffers comprises;
a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased;
a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased;
a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify; and
a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify.
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Accused Products
Abstract
Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit lines through a sensing line. Each of the plurality of page buffers may include a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify, and a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify.
20 Citations
7 Claims
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1. A non-volatile memory device, comprising:
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a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines; and
a plurality of page buffers connected to the bit lines through a sensing line,each of the plurality of page buffers comprises;
a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased;
a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased;
a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify; and
a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification