Non-volatile semiconductor memory device

• US 20060291291A1
• Filed: 06/20/2006
• Published: 12/28/2006
• Est. Priority Date: 06/22/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Hiroshi, Hosono, Koji
• Granted Patent: US 7,492,641 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A non-volatile semiconductor memory device includes a memory cell array and a sense amplifier, the device being internally controlled to execute a write sequence with write pulse applications and write-verify operations repeated for writing a set of memory cells selected in the memory cell array, wherein the sense amplifier performs a write speed verify operation for detecting write speed of plural memory cells to be written into a certain data state after a certain write pulse application at the beginning of the write sequence, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, and after the write speed verify operation, the first and second cell groups are alternately written on different write conditions from each other with reference to the discriminating data.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array having electrically rewritable and non-volatile semiconductor memory cells arranged therein; and

a sense amplifier circuit configured to read data of and hold data to be written into the memory cell array, the device being internally controlled to execute a write sequence with write pulse applications and write-verify operations repeated for writing a set of memory cells selected in the memory cell array, wherein

the sense amplifier circuit performs a write speed verify operation for detecting write speed of plural memory cells to be written into a certain data state after a certain write pulse application at the beginning of the write sequence, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group, and wherein

after the write speed verify operation, the first and second cell groups are alternately written on different write conditions from each other with reference to the discriminating data.

2. The non-volatile semiconductor memory device according to claim 1, wherein

a first write pulse application for writing the first cell group and a second write pulse application for writing the second cell group are sequentially performed, the first and second write pulses being different in voltage from each other, following it a write verify operation is performed for both of the first and second cell groups on the same condition at a time.

3. The non-volatile semiconductor memory device according to claim 1, wherein

after the write speed verify operation, write data transferred to the first and second cell groups are alternately inverted based on the discriminating data held in the sense amplifier circuit.

4. The non-volatile semiconductor memory device according to claim 1, wherein

after the write-verify operation, a write-completion detection is performed for detecting whether the entire selected memory cells have been written or not.

5. The non-volatile semiconductor memory device according to claim 4, wherein

the write-completion detection is performed during the write pulse application.

6. The non-volatile semiconductor memory device according to claim 1, wherein

after the write verify operation, write-completion detections are performed with respect to the first and second cell groups, respectively, for detecting whether the memory cells have been written or not, and after the write-completion has been detected for one cell group, the write pulse application is successively performed for only the other cell group.

7. The non-volatile semiconductor memory device according to claim 6, wherein

the write-completion detections are performed during the write pulse applications for the first and second cell groups, respectively.

8. The non-volatile semiconductor memory device according to claim 1, wherein

the memory cell array has NAND cell units arranged therein, each NAND cell unit having plural memory cells connected in series and select gate transistors disposed at the both ends thereof.

9. The non-volatile semiconductor memory device according to claim 1, wherein

the sense amplifier circuit has plural sense units for simultaneously reading data of or simultaneously writing data into the set of memory cells selected in the memory cell array, and wherein each the sense unit includes:

a first data latch, in which write data is loaded;

a write-back circuit disposed in association with the first data latch for writing-back write data of the next write cycle into the first data latch based on the write verify-read data;

a second data latch disposed in parallel with the first data latch, to which the write data loaded in the first data latch is transferred at the beginning of the write sequence, and the discriminating data obtained by the write speed verify operation is held in;

a write speed switching circuit disposed in association with the second data latch, which serves for switching bit line control voltage for the purpose of alternately writing the first and second cell groups based on the discriminating data held in the second data latch; and

a bit line drive circuit, which is so controlled by data held in the first and second data latches as to generate a bit line control voltage required at a data write time in corporation with the write speed switching circuit.

10. The non-volatile semiconductor memory device according to claim 9, further comprising a write-completion detection circuit, which checks write data held in the first data latch with reference to the discriminating data held in the second data latch in each the sense unit to detect write-completion for each of the first and second cell groups.

11. The non-volatile semiconductor memory device according to claim 10, wherein the write-completion detection circuit has plural completion detection units for detecting write-completion in the entire sense units, each write-completion detection unit serving for detecting write-completion in plural sense units.

12. The non-volatile semiconductor memory device according to claim 1, wherein

the write sequence is for writing at least two, first and second, data states simultaneously into the set of memory cells, and wherein

the sense amplifier circuit performs a write speed verify operation for detecting write speed of plural memory cells to be written into at least the first data state after a certain write pulse application at the beginning of the write sequence, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group, and wherein

after the write speed verify operation, the first and second cell groups are alternately written on different write conditions from each other with reference to the discriminating data.

13. The non-volatile semiconductor memory device according to claim 12, wherein

the first and second data states are defined by a first threshold distribution and a second threshold distribution higher than the first threshold distribution, respectively;

in the write cycle of the first data state, the first and second cell groups are alternately written with first and second write pulses each sequentially stepped-up, the second write pulses being higher than the first write pulses, and a first write-verify operation is performed after each of the first and second write pulse applications on the same condition at a time; and

wherein

data write in the former half of a write cycle of the second data state is performed with the second write pulses in the write cycle of the first data state, and a second write-verify operation thereof is performed as following the first write verify operation while data write in the latter half thereof is performed with third write pulses as following the second write pulses and third write-verify operations repeated.

14. The non-volatile semiconductor memory device according to claim 13, wherein

write-completion detections for the first data state are performed during the first and second write pulse applications for the first and second cell groups, respectively, within the memory cells to be written into the first data state in the write cycle of the first data state;

and wherein

write-completion detections for the second data state are performed during each the second write pulse application in the former half while during each the third write pulse application in the latter half.

15. The non-volatile semiconductor memory device according to claim 1, wherein

the write sequence is for writing at least three, first, second and third, data states simultaneously into the set of memory cells, the three data states being arranged in order of the threshold voltage height, and wherein

the sense amplifier circuit performs a first write speed verify operation for detecting write speed of memory cells to be written into the first data state after a certain write pulse application at the beginning of the write sequence, thereby getting first discriminating data for classifying the memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group, and performs a second write speed verify operation for detecting write speed of memory cells to be written into the third data state halfway in the write sequence, thereby getting second discriminating data for classifying the memory cells into third and fourth cell groups, the write speed of the fourth cell group being lower than that in the third cell group;

in the former half of the write sequence, the first and second cell groups are alternately written with first and second write pulses, respectively, in the memory cells to be written into the first data state with reference to the first discriminating data, the second write pulses being higher than the first write pulses;

in the latter half of the write sequence, the third and fourth cell groups are alternately written with third and fourth write pulses, respectively, in the memory cells to be written into the third data state with reference to the second discriminating data, the fourth write pulses being higher than the third write pulses; and

the second write pulses applied to the second cell group and the third write pulses applied to the third cell group are used for writing the memory cells to be written into the second data state.

16. A method of writing data into a set of memory cells in a non-volatile semiconductor memory device with write pulse applications and write-verify operations repeated, comprising:

performing a write speed verify operation for detecting write speed of plural memory cells to be written into a certain data state after a certain write pulse application at the beginning of a write sequence, thereby getting discriminating data for classifying the plural memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group; and

alternately writing the first and second cell groups on different write conditions from each other with reference to the discriminating data after the write speed verify operation.

17. The method of writing data according to claim 16, wherein

the write sequence is for writing at least two, first and second, data states simultaneously into the set of memory cells;

the write speed verify operation is performed for detecting write speed of memory cells to be written into at least the first data state;

with respect to the memory cells to be written into the first data state, the first and second cell groups are alternately written with first and second write pulses, respectively, which are stepped-up as being different from each, with reference to the discriminating data, after the write speed verify operation; and

memory cells to be written into the second data state are written with the second write pulses simultaneously with the second cell group, and successively written with third write pulses stepped-up.

18. The method of writing data according to claim 16, wherein the write sequence is for writing at least three, first, second and third, data states simultaneously into the set of memory cells, the three data states being arranged in order of the threshold voltage height;

a first write speed verify operation is performed for detecting write speed of memory cells to be written into the first data state after a certain write pulse application at the beginning of the write sequence, so as to get first discriminating data for classifying the memory cells into first and second cell groups, the write speed of the memory cell in the second cell group being lower than that in the first cell group;

in the former half of the write sequence, the first and second cell groups are alternately written with first and second write pulses, respectively, in the memory cells to be written into the first data state with reference to the first discriminating data, the second write pulses being higher than the first write pulses;

a second write speed verify operation is performed for detecting write speed of memory cells to be written into the third data state halfway in the write sequence, so as to get second discriminating data for classifying the memory cells into third and fourth cell groups, the write speed of the fourth group being lower than that in the third cell group;

in the latter half of the write sequence, the third and fourth cell groups are alternately written with third and fourth write pulses, respectively, in the memory cells to be written into the third data state with reference to the second discriminating data, the fourth write pulses being higher than the third write pulses; and

the second write pulses applied to the second cell group and the third write pulses applied to the third cell group are used for writing the memory cells to be written into the second data state.