Bias circuits and methods for enhanced reliability of flash memory device

• US 20060291293A1
• Filed: 12/28/2005
• Published: 12/28/2006
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Young-Ho, Chae, Dong-Hyuk
• Granted Patent: US 7,433,235 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

Claims

1. A non-volatile semiconductor memory device comprising:

cell strings connected to respective bit lines;

each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor;

a first voltage drop circuit configured to reduce an applied read voltage during a read operation;

a second voltage drop circuit configured to reduce the applied read voltage;

a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and

a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

2. The non-volatile semiconductor memory device of claim 1, wherein the reduced voltage provided by the first voltage drop circuit is the same as the reduced voltage provided by the second voltage drop circuit.

3. The non-volatile semiconductor memory device of claim 1, wherein the reduced voltage provided by the first voltage drop circuit is higher than the reduced voltage provided by the second voltage drop circuit.

4. The non-volatile semiconductor memory device of claim 1, wherein the reduced voltage provided by the first voltage drop circuit is lower than the reduced voltage provided by the second voltage drop circuit.

5. The non-volatile semiconductor memory device of claim 1, wherein each of the first and second voltage drop circuits is configured to reduce the read voltage by 2 Vth, where Vth is a threshold voltage of an NMOS transistor.

6. The non-volatile semiconductor memory device of claim 1, wherein each of the first and second voltage drop circuits is configured to reduce the read voltage by N*Vth, where N is an integer and Vth is a threshold voltage of an NMOS transistor.

7. A non-volatile semiconductor memory device having a plurality of memory blocks each including first transistors for selecting a plurality of word lines and second transistors for selecting string select lines and ground select lines, the device further comprising:

a charge pump configured to generate a read voltage during a read operation;

a voltage regulator configured to control the charge pump so that the read voltage is maintained at a constant level;

a first driver circuit configured to transfer the read voltage to the first transistors during the read operation;

a voltage drop circuit configured to reduce the read voltage from the charge pump to generate a reduced voltage; and

a second driver circuit configured to transfer the reduced voltage to the second transistors during the read operation.

8. The non-volatile semiconductor memory device of claim 7, wherein the voltage drop circuit reduces the read voltage by a voltage that corresponds to a sum of threshold voltages of plural transistors.

9. The non-volatile semiconductor memory device of claim 7, wherein the voltage drop circuit includes first and second voltage drop portions for reducing the read voltage,

an output voltage of the first voltage drop portion being applied to the string select line by the second driver circuit and an output voltage of the second voltage drop portion being applied to the ground select line by the second driver circuit.

10. The non-volatile semiconductor memory device of claim 9, wherein the output voltage of the first voltage drop portion is identical to the output voltage of the second voltage drop portion.

11. The non-volatile semiconductor memory device of claim 9, wherein the output voltage of the first voltage drop portion is higher than the output voltage of the second voltage drop portion.

12. The non-volatile semiconductor memory device of claim 9, wherein the output voltage of the first voltage drop portion is lower than the output voltage of the second voltage drop portion.

13. The non-volatile semiconductor memory device of claim 9, wherein each of the first and second voltage drop parts is configured to reduce the read voltage by 2 Vth, where Vth is a threshold voltage of an NMOS transistor.

14. A read voltage supplying method in a non-volatile semiconductor memory device which comprises cell strings connected to respective bit lines, each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected between the select transistors and connected to corresponding word lines, the method comprising:

generating a read voltage to be supplied to unselected word lines;

reducing the read voltage by a predetermined voltage;

supplying the reduced read voltage to the string select lines and ground select lines in response to a control signal indicating a read operation; and

supplying the read voltage to the unselected word lines and a ground voltage to a selected word line in response to the control signal.

15. The method of claim 14, wherein the reduced read voltage is reduced by 2 Vth, where Vth is a threshold voltage of an NMOS transistor.

16. The method of claim 14, wherein the read voltage is reduced by N*Vth, where N is an integer and Vth is a threshold voltage of an NMOS transistor.