Serial protocol for agile sample rate switching

• US 20060291545A1
• Filed: 08/17/2005
• Published: 12/28/2006
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Lau, King-Hon, Simmonds, Harold T., Yoder, James D., Ransijn, Johannes G.
• Granted Patent: US 8,213,489 B2
• Time in Patent Office: Days
• US Class Current: 375/220
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals
• CPC Class Codes: H04M 3/005 Interface circuits for subscriber lines current supply H04M19/00 and subgroups; supervisory, monitoring or testing arrangements H04M3/22 and subgroups; in key telephone systems H04M9/006

Abstract

The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ΣΔ rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Claims

1. A method for selecting an interface clock rate for a variable-rate serial interface, comprising the steps of:

identifying two or more communication rates for communication of data across the interface;

calculating an approximate common multiple of the two or more communication rates; and

selecting the approximate common multiple as the interface clock rate.

2. The method of claim 1, wherein the two or more communication rates are symbol rates selected from the group consisting of 2400, 2743, 2800, 3000, 3200, and 3429.

3. The method of claim 1, wherein the two or more communication rates are sample rates selected from the group consisting of 7200, 8000, 8229, 8400, 9000, 9660, 10287, and 11025 samples per second.

4. The method of claim 1, where the two or more communication rates are sigma-delta rates selected from the group consisting of 1.843, 2.048, 2.107, 2.150, 2.204, 2.458, 2.634, and 2.822 MHz.

5. The method of claim 1, wherein the approximate greatest common denominator of the two or more communication rates is one of about 33.3 MHz and about 36 MHz.

6. The method of claim 1, further comprising the steps of:

defining a plurality of frames, each frame corresponding to at least one of the two or more communication rates and having a frame length.

7. The method of claim 6, wherein the frame length for each of the plurality of frames is obtained by dividing the approximate common multiple of the two or more communication rates by the respective communication rate.

8. The method of claim 7, wherein the frame length for each of the plurality of frames is one of (i) between about 12 and about 18 clock cycles and (ii) between about 13 and about 20 clock cycles.

9. The method of claim 6, further including the step of adjusting the interface clock rate for each of the two or more communication rates to the rate obtained by multiplying each communication rate by its corresponding frame length, thereby yielding two or more customized interface clock rates that correspond respectively to the two or more communication rates.

10. The method of claim 9, wherein the two or more customized interface clock rates are within one of (i) the range of about 32 MHz to about 35 MHz and (ii) the range of about 35 MHz to about 37 Mhz.

11. The method of claim 10, wherein the two or more customized interface clock rates are selected from one of (i) the group consisting of 33.1776, 32.7680, 33.7056, 32.2560, 34.4064, 34.2355, and 33.8688 MHz and (ii) the group consisting of 36.864, 36.864, 35.813, 36.557, 36.864, 36.864, 36.869 and 36.691 MHz.

12. A method for communicating data at multiple communication rates over a serial interface having an approximately fixed interface clock rate, comprising the steps of:

receiving a first rate select signal indicating a first communication rate;

transmitting over the serial interface a first frame including a first datum and a first quantity of padding bits corresponding to the first communication rate, at the approximately fixed interface clock rate;

receiving a second rate select signal indicating a second communication rate;

transmitting over the serial interface a second frame including a second datum and a second quantity of padding bits corresponding to the second communication rate, at the approximately fixed interface clock rate;

whereby the first datum is communicated at a rate corresponding to the first communication rate and the second datum is communicated at a rate corresponding to the second communication rate.

13. The interface circuit of claim 12, wherein each of the first and second communication rates is a symbol rate selected from the group consisting of 2400, 2743, 2800, 3000, 3200, and 3429.

14. The interface circuit of claim 12, wherein each of the first and second communication rates is a sample rate selected from the group consisting of 7200, 8000, 8229, 8400, 9000, 9660, 10287, and 11025 samples per second.

15. The interface circuit of claim 12, wherein each of the first and second communication rates are sigma-delta rates selected from the group consisting of 1.843, 2.048, 2.107, 2.150, 2.204, 2.458, 2.634, and 2.822 MHz.

16. The method of claim 12, wherein the approximately fixed interface clock rate is an approximate common multiple of the first and second communication rates.

17. The method of claim 12, further comprising the steps of

adjusting the approximately fixed interface clock rate based on the first communication rate, before transmitting the first frame;

and

adjusting the approximately fixed interface clock rate based on the second communication rate, before transmitting the second frame.

18. The method of claim 17, wherein the approximately fixed interface clock rate is adjustable within one of (i) the range from about 32 MHz to about 35 MHz, and (ii) the range from about 35 MHz to about 37 MHz.

19. The method of claim 17, wherein the approximately fixed interface clock rate is selected from one of (i) the group consisting of 33.1776, 32.7680, 33.7056, 32.2560, 34.4064, 34.2355, and 33.8688 MHz and (ii) the group consisting of 36.864, 36.864, 35.813, 36.557, 36.864, 36.864, 36.869 and 36.691 MHz.

20. The method of claim 12, wherein the first and second frames further include a framing sequence.

21. The method of claim 20, wherein the first and second datum are Manchester encoded and wherein the framing sequence is three consecutive bits of same value during three consecutive clock cycles at the approximately fixed interface clock rate.

22. The method of claim 12, wherein each of the first quantity of padding bits and the second quantity of padding bits is one of (i) an integer number between 0 and 6, and (ii) and integer number between about 0 and 7.

23. A method for transmitting and receiving information across a serial interface during a single TDM frame of the serial interface, comprising the steps of:

transmitting a forward data bit across the serial interface during a first time slot in the TDM frame;

transmitting a forward control bit across the serial interface during a second time slot in the TDM frame;

transmitting a predetermined forward framing sequence during a third time slot in the TDM frame

receiving a reverse data bit during a fourth time slot in the TDM frame; and

receiving a reverse control bit during a fifth time slot in the TDM frame.

24. The method of claim 23, wherein the serial interface employs Manchester encoding, and wherein the predetermined forward framing sequence is represented by a one of a “

111”

bit pattern or a “

000”

bit pattern during three consecutive clock cycles of the serial interface.

25. The method of claim 23, further comprising the step of transmitting a quantity of padding bits in the TDM frame.

26. The method of claim 25, further comprising the step of determining the quantity of padding bits based on a desired communication rate.

27. The method of claim 26, wherein the step of determining a quantity of padding bits comprises the steps of:

receiving a signal indicating the desired communication rate; and

looking up the desired communication rate in a look-up table to obtain the quantity of padding bits corresponding to the desired communication rate.

28. An agile communication circuit capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate, comprising:

a processor, configured to select a communication rate and a frame length corresponding to the selected communication rate; and

a framer circuit, connected to the processor and configured to receive data from the processor and to insert the data into at least one variable-length frame for transmission over the serial interface, the length of the at least one variable-length frame being based on the selected frame length,

wherein the length of the at least one variable-length frame determines the communication rate of the serial interface, and

wherein the interface clock rate remains approximately fixed and approximately independent of the selected communication rate.

29. The communication circuit of claim 28, wherein the communication rate is a symbol rate selected from the group consisting of 2400, 2743, 2800, 3000, 3200, and 3429.

30. The communication circuit of claim 28, wherein the communication rate is a sample rate selected from the group consisting of 7200, 8000, 8229, 8400, 9000, 9660, 10287, and 11025 samples per second.

31. The communication circuit of claim 28, wherein the two or more communication rates are sigma-delta rates selected from the group consisting of 1.843, 2.048, 2.107, 2.150, 2.204, 2.458, 2.634, and 2.822 MHz.

32. The communication circuit of claim 28, wherein the approximately fixed interface clock rate is within one of (i) the range of about 32 MHz to about 35 MHz and (ii) the range of about 35 MHz to about 37 Mhz.

33. The communication circuit of claim 28, wherein the selected frame length is one of (i) between about 12 and about 18 interface clock cycles and (ii) between about 13 and about 20 interface clock cycles.

34. The communication circuit of claim 28, wherein the framer circuit is configured to insert a predetermined quantity of padding bits in each at least one variable-length frame.

35. The communication circuit of claim 28, further comprising

a frame-length lookup table correlating frame length with communication rate, and

wherein the processor is further configured to select a frame length by looking up the selected communication rate in the lookup table.

36. The communication circuit of claim 28, further comprising

a variable-rate interface clock generator connected to the processor, and

wherein the processor is further configured to select a customized interface clock rate based on the communication rate and to pass the customized clock rate to the variable-rate interface clock generator.

37. The communication circuit of claim 36, wherein the customized interface clock rate is selected from one of (i) the group consisting of 33.1776, 32.7680, 33.7056, 32.2560, 34.4064, 34.2355, and 33.8688 MHz and (ii) the group consisting of 36.864, 36.864, 35.813, 36.557, 36.864, 36.864, 36.869 and 36.691 MHz.

38. The communication circuit of claim 36, further comprising

a clock-rate lookup table correlating clock rate with communication rate,

wherein the processor is configured to select the customized interface clock rate by looking up the selected communication rate in the clock-rate lookup table.

39. The communication circuit of claim 36, wherein the variable-rate clock generator includes

a barrier clock controller capable of producing a voltage corresponding to the selected customized interface clock rate;

and

a voltage-controlled oscillator connected to receive the voltage produced by the barrier clock controller and to produce a clock signal having the selected customized interface clock rate, for use as the interface clock signal.

40. A method for identifying a frame break in a TDM interface employing Manchester encoding, comprising:

transmitting or receiving one of a “

111”

bit pattern or a “

000”

bit pattern during three consecutive clock cycles of the TDM interface employing Manchester encoding.