Method and apparatus for a fully digital quadrature modulator

• US 20060291589A1
• Filed: 08/11/2005
• Published: 12/28/2006
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cruise, Francis P., Staszewski, Robert B., Eliezer, Oren E., Mehta, Jaimin
• Granted Patent: US 7,460,612 B2
• Time in Patent Office: Days
• US Class Current: 375/302
• CPC Class Codes: H03C 3/40 using two signal paths the outputs of which have a predetermined phase difference and at least one output being amplitude-modulated
• CPC Class Codes: H03C 5/00 Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal H03C7/00 takes precedence
• CPC Class Codes: H03F 2200/324 An amplitude modulator or demodulator being used in the amplifier circuit
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04K 1/02 by adding a second signal to make the desired signal unintelligible
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/2092 with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier)
• CPC Class Codes: H04L 27/365 Modulation using digital generation of the modulated carrier (not including modulation of a digitally generated carrier)

Abstract

A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

Claims

1. A digital complex modulator, comprising:

a first parallel array of switches adapted to be clocked by an I local oscillator clock signal gated with an I digital control word to generate a first current therefrom substantially proportional to said I digital control word;

a second parallel array of switches adapted to be clocked by a Q local oscillator clock signal gated with a Q digital control word to generate a second current therefrom substantially proportional to said Q digital control word; and

means for summing said first current and said second current to yield a complex modulated output signal.

2. The modulator according to claim 1, wherein said first parallel array of switches and said second parallel array of switches each comprises an array of transistors.

3. The modulator according to claim 1, wherein said first parallel array of switches and said first parallel array of switches each comprises a differential array of transistors adapted to generate a differential signal.

4. The modulator according to claim 1, wherein said I local oscillator clock signal and said Q local oscillator clock signal are 90 degrees phase shifted from each other.

5. The modulator according to claim 1, wherein said I digital control signal comprises an in-phase component of a complex-envelope baseband signal and said Q digital control signal comprises a quadrature phase component of a complex-envelope baseband signal.

6. The modulator according to claim 1, further comprising a filter or matching network adapted to receive said output signal and generate a filtered RF output signal therefrom.

7. The modulator according to claim 1, wherein said complex modulated output signal is employed in a multi-mode or software defined radio adapted to operate in accordance with a communications standard selected from a plurality of communications standards supported by said radio.

8. The modulator according to claim 1, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

9. The modulator according to claim 1, adapted to be implemented in a Field Programmable Gate Array (FPGA).

10. A method of digital I/Q complex modulation, said method comprising the steps of:

providing an I switch array adapted to generate a first signal proportional to the number of switches active within said I switch array;

providing a Q switch array adapted to generate a second signal proportional to the number of switches active within said Q switch array;

applying a first gated combination of an I local oscillator clock signal and an I digital control word to said I switch array whereby the number of switches active in said I switch array is determined by said I control word;

applying a second gated combination of a Q local oscillator clock signal and a Q digital control word to said Q switch array whereby the number of switches active in said Q switch array is determined by said Q control word; and

summing said first signal and said second signal to yield a complex modulated output signal therefrom.

11. The method according to claim 10, wherein said I switch array and said Q switch array each comprises an array of transistors.

12. The method according to claim 10, wherein said I switch array and said Q switch array each comprises a differential array of transistors adapted to generate a differential signal.

13. The method according to claim 10, wherein said I local oscillator clock signal and said Q local oscillator clock signal are 90 degrees phase shifted from each other.

14. The method according to claim 10, wherein said I control signal and said Q control signal comprise in-phase and quadrature phase components of a complex-envelope baseband signal, respectively.

15. The method according to claim 10, further comprising the step of applying said output signal to a filter or matching network adapted to generate a filtered RF output signal therefrom.

16. The method according to claim 10, wherein said complex modulated output signal is employed in a multi-mode or software defined radio adapted to operate in accordance with a communications standard selected from a plurality of communications standards supported by said radio.

17. The method according to claim 10, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

18. The method according to claim 10, adapted to be implemented in a Field Programmable Gate Array (FPGA).

19. A digital quadrature modulator, comprising:

a local oscillator operative to generate quadrature phases;

a switch array comprising a plurality of switches adapted to generate a complex modulated output signal substantially proportional to the number of switches active at any one time in said array;

a switch matrix adapted to couple said quadrature phases output of said local oscillator to said transistor array; and

control means coupled to said switch array, said control means operative to dynamically allocate a first portion of said switches to I output and a second portion to Q output based on values of I and Q input signals.

20. The modulator according to claim 19, wherein said plurality of switches comprises a plurality of transistors.

21. The modulator according to claim 19, wherein said switch matrix further comprises a plurality of attenuators, each attenuator adapted to be coupled to a switch in said switch array when none of said quadrature phases are selected to be coupled thereto.

22. The modulator according to claim 19, wherein said complex modulated output signal is employed in a multi-mode or software defined radio adapted to operate in accordance with a communications standard selected from a plurality of communications standards supported by said radio.

23. The modulator according to claim 19, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

24. The modulator according to claim 19, adapted to be implemented in a Field Programmable Gate Array (FPGA).

25. A digital quadrature modulator, comprising:

oscillator means for generating a local oscillator I (LO_I) signal, an inverted {overscore (LO_I)} signal, a LO_Q signal, and an inverted {overscore (LO_Q)} signal;

an I switch array comprising a plurality of first switches adapted to generate an I output signal substantially proportional to a number of first switches active at any one time, wherein the number of first switches active in synchronization with the LO_I or {overscore (LO_I)} signal is determined by a magnitude of an I digital input signal;

a Q switch array comprising a plurality of second switches adapted to generate a Q output signal substantially proportional to the number of second switches active at any one time, wherein the number of second switches active in synchronization with the LO_Q or {overscore (LO_Q)} signal is determined by a magnitude of a Q digital input signal;

first means adapted to couple either said LO_I signal or said {overscore (LO_I)} signal to said I switch array in accordance with a sign of said I input signal;

second means adapted to couple either said LO_Q signal or said {overscore (LO_Q)} signal to said Q switch array in accordance with a sign of said Q input signal; and

means for summing said I output signal and said Q output signal to generate a quadrature modulated output therefrom.

26. The modulator according to claim 25, wherein said plurality of first switches and said plurality of second switches each comprises a plurality of transistors.

27. The modulator according to claim 25, wherein said I switch array and said Q switch array each comprises a separate plurality of unit-weighted transistors adapted to receive a thermometer coded digital input signal.

28. The modulator according to claim 25, wherein said I switch array and said Q switch array each comprises a separate plurality of binary-weighted transistors adapted to receive a naturally encoded digital input signal.

29. The modulator according to claim 25, wherein said quadrature modulated output is employed in a multi-mode or software defined radio adapted to operate in accordance with a communications standard selected from a plurality of communications standards supported by said radio.

30. The modulator according to claim 25, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

31. The modulator according to claim 25, adapted to be implemented in a Field Programmable Gate Array (FPGA).

32. A digital quadrature modulator, comprising:

oscillator means for generating a first local oscillator signal LO_I, a second local oscillator signal LO′

_I, a third local oscillator signal LO_Q, and fourth local oscillator signal LO′

_Q;

a switch array comprising a plurality of switches adapted to be shared between I and Q digitally control branches, said switch array operative to generate a quadrature modulated output signal substantially proportional to a number of switches instantaneously active in accordance with the combined I and Q input digital signals and said local oscillator signals;

first means for generating an I contribution in accordance with an I input signal and an I local oscillator signal;

second means for generating a Q contribution in accordance with an I input signal and an I local oscillator signal; and

third means for time multiplexing said I contribution and said Q contribution to yield said combined I and Q signal to produce said quadrature modulated output.

33. The modulator according to claim 32, wherein said first means comprises:

fourth means adapted to couple either said LO_I signal or said LO′

_I signal to a first plurality of gates in accordance with a sign of said I input signal; and

said first plurality of gates adapted to gate said I input signal with said LO_I signal or said LO′

_I signal to generate said I contribution therefrom.

34. The modulator according to claim 32, wherein said second means comprises:

fourth means adapted to couple either said LO_Q signal or said LO′

_Q signal to a first plurality of gates in accordance with a sign of said Q input signal; and

said second plurality of gates adapted to gate said Q input signal with said LO_Q signal or said LO′

_Q signal to generate said Q contribution therefrom.

35. The modulator according to claim 32, wherein said plurality of switches comprises a plurality of transistors.

36. The modulator according to claim 32, wherein said switch array comprises a plurality of unit-weighted transistors adapted to receive a thermometer coded combined I and Q signal.

37. The modulator according to claim 32, wherein said switch array comprises a plurality of binary-weighted transistors adapted to receive a naturally encoded combined I and Q signal.

38. The modulator according to claim 32, wherein said quadrature modulated output is employed in a multi-mode or software defined radio adapted to operate in accordance with a communications standard selected from a plurality of communications standards supported by said radio.