Semiconductor processing methods

• US 20060292793A1
• Filed: 06/24/2005
• Published: 12/28/2006
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Sukesh, Hurley, Kelly T.
• Granted Patent: US 7,271,060 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor substrate and components of a peripheral region proximate the memory array region, and yet the components of the peripheral region are built for different performance characteristics than the components of the memory array region. The methods can include laterally recessing nitride-containing masking structures associated with the peripheral region to a greater extent than nitride-containing masking structures associated with the memory array region, followed by thermal oxidation of the substrate to form dielectric material adjacent the masking structures.

Claims

1. A semiconductor processing method, comprising:

providing a semiconductor substrate comprising a memory array region and a peripheral region proximate the memory array region;

forming spaced nitride-containing masking structures over the substrate, some of the nitride-containing masking structures being first nitride-containing masking structures over the memory array region and others of the nitride-containing masking structures being second nitride-containing masking structures over the peripheral region;

forming trenches in the substrate between the spaced nitride-containing masking structures, some of the trenches being first trenches associated with the memory array region and others being second trenches associated with the peripheral region, the second trenches being formed to be substantially deeper than the first trenches;

after forming the first and second trenches, laterally recessing the second nitride-containing masking structures to a degree greater than any lateral recessing of the first nitride-containing masking structures; and

after the lateral recessing of the second nitride-containing masking structures, oxidizing the substrate within the first and second trenches, and then depositing insulative material within the first and second trenches.

2. The method of claim 1 wherein the there is no lateral recessing of the first nitride-containing structures during said lateral recessing of the second nitride-containing structures.

3. The method of claim 1 wherein the lateral recessing of the second nitride-containing structures is a second lateral recessing;

wherein the oxidizing of the substrate within the first and second trenches is a second oxidizing; and

further comprising;

initially forming the first and second trenches to be about the same depth as one another;

after the initial formation of the first and second trenches, first laterally recessing the first and second nitride-containing masking structures;

after the first lateral recessing of the first and second nitride-containing masking structures;

first oxidizing the substrate to form a first oxide layer extending within the first and second trenches;

forming protective material within the first trenches and over the first oxide layer within the first trenches; and

while the protective material is within the first trenches, removing at least some of the first oxide layer from within the second trenches and then extending the second trenches to be substantially deeper than the first trenches.

4. The method of claim 3 wherein:

the nitride-containing masking structures have exposed nitride-containing lateral surfaces during the first oxidizing of the substrate to form the first oxide layer extending within the first and second trenches; and

the first oxidation comprises dry thermal oxidation and does not appreciably oxidize the exposed nitride-containing lateral surfaces.

5. The method of claim 4 wherein:

the protective material within the first trenches extends to over the first nitride-containing masking structures and covers the nitride-containing lateral surfaces of the first nitride-containing masking structures; and

the protective material remains within the first trenches and over the nitride-containing lateral surfaces of the first nitride-containing masking structures during the second lateral recessing.

6. The method of claim 3 wherein:

the nitride-containing masking structures have exposed nitride-containing lateral surfaces during the first oxidizing of the substrate to form the first oxide layer extending within the first and second trenches; and

the first oxidation comprises wet thermal oxidation and forms some of the oxide from the exposed nitride-containing lateral surfaces.

7. The method of claim 6 wherein the protective material within the first trenches is removed prior to the second lateral recessing.

8. The method of claim 6 wherein the protective material within the first trenches is removed after the second lateral recessing.

9. The method of claim 1 wherein the second trenches are spaced from one another by mesas of semiconductor material of the substrate having the second nitride-containing structures thereover;

wherein the oxidizing of the substrate within the second trenches forms rounded upper corners of the mesas; and

further comprising;

after the oxidizing, removing the second nitride-containing structures from over the mesas;

forming dielectric material over the mesas; and

forming electrically conductive material over the dielectric material.

10. The method of claim 9 wherein the dielectric material and electrically conductive material are together incorporated into a plurality of spaced lines.

11. The method of claim 9 wherein the mesas are second mesas;

wherein the first trenches are spaced from one another by first mesas of the semiconductor material having the first nitride-containing structures thereover;

wherein the first nitride-containing structures are removed from over the first mesas simultaneously with the removal of the second nitride-containing structures; and

further comprising forming a plurality of wordlines extending across the first mesas.

12. A semiconductor processing method, comprising:

providing a semiconductor substrate comprising a memory array region and a peripheral region proximate the memory array region;

forming spaced masking stacks over the memory array region and the peripheral region, the masking stacks comprising a nitride-containing layer and an oxide-containing layer over the nitride-containing layer;

forming trenches extending into the substrate between the spaced masking stacks, some of the trenches being first trenches associated with the memory array region and others being second trenches associated with the peripheral region;

extending the second trenches deeper into the substrate while protecting the first trenches with a protective material provided within the first trenches;

after extending the second trenches, laterally recessing the nitride-containing layer of the masking stacks over the peripheral region;

removing the protective material from within the first trenches; and

after laterally recessing the nitride-containing layer, oxidizing the substrate within the first and second trenches, and then filling the first and second trenches with insulative material.

13. The method of claim 12 wherein the protective material is removed prior to the lateral recessing of the nitride-containing layer of the masking stacks over the peripheral region.

14. The method of claim 12 wherein the protective material is removed after the lateral recessing of the nitride-containing layer of the masking stacks over the peripheral region.

15. The method of claim 12 wherein the lateral recessing of the nitride-containing layer is a second lateral recessing;

wherein the oxidizing of the substrate within the first and second trenches is a second oxidizing; and

further comprising;

after forming the first and second trenches and prior to providing the protective material within the first trenches, first laterally recessing the nitride-containing layer;

after the first lateral recessing of the nitride-containing layer;

first oxidizing the substrate to form a first oxide layer extending within the first and second trenches;

forming the protective material within the first trenches to be over the first oxide layer within the first trenches; and

while the protective material is within the first trenches, removing at least some of the first oxide layer from within the second trenches and then performing the extending of the second trenches to be deeper into the substrate.

16. The method of claim 15 wherein:

the nitride-containing layer of the masking stacks has exposed nitride-containing lateral surfaces during the first oxidizing of the substrate to form the first oxide layer extending within the first and second trenches; and

the first oxidation comprises dry thermal oxidation and does not appreciably oxidize the exposed nitride-containing lateral surfaces.

17. The method of claim 16 wherein:

the protective material within the first trenches extends to over the nitride-containing layer of the masking stacks of the memory array region and covers the nitride-containing lateral surfaces of the nitride-containing layer of the masking stacks of the memory array region; and

the protective material remains within the first trenches and over the nitride-containing lateral surfaces of the nitride-containing layer of the masking stacks of the memory array region during the second lateral recessing.

18. The method of claim 15 wherein:

the nitride-containing layer of the masking stacks has exposed nitride-containing lateral surfaces during the first oxidizing of the substrate to form the first oxide layer extending within the first and second trenches; and

the first oxidation comprises wet thermal oxidation and forms some of the oxide from the exposed nitride-containing lateral surfaces.

19. The method of claim 18 wherein the protective material within the first trenches is removed prior to the second lateral recessing.

20. The method of claim 18 wherein the protective material within the first trenches is removed after the second lateral recessing.

21. The method of claim 12 wherein the second trenches are spaced from one another by mesas of semiconductor material of the substrate having the masking stacks thereover;

wherein the oxidizing of the substrate within the second trenches forms rounded upper corners of the mesas; and

further comprising;

after the oxidizing, removing the masking stacks from over the mesas;

forming dielectric material over the mesas; and

forming electrically conductive material over the dielectric material.

22. The method of claim 21 wherein the dielectric material and electrically conductive material are together incorporated into a plurality of spaced lines.

23. A semiconductor processing method, comprising:

providing a semiconductor substrate comprising a memory array region and a peripheral region proximate the memory array region;

forming a stack over the peripheral and memory array regions of the substrate;

the stack comprising, in ascending order, a nitride-containing layer, oxide-containing layer, carbon-containing layer, and anti-reflective coating;

forming a patterned photoresist mask over the stack;

transferring a pattern from the photoresist mask to the oxide-containing layer and the nitride-containing layer to form spaced masking stacks comprising the patterned nitride-containing layer and patterned oxide-containing layer;

removing the carbon-containing layer, anti-reflective coating and patterned photoresist mask;

forming trenches extending into the substrate between the spaced masking stacks, some of the trenches being first trenches associated with the memory array region and others being second trenches associated with the peripheral region;

forming a protective material over the memory array region;

while the protective material is over the memory array region, extending the second trenches deeper into the substrate;

removing the protective material;

after extending the second trenches, laterally recessing the nitride-containing layer of the masking stacks over the peripheral region; and

after laterally recessing the nitride-containing layer and removing the protective material, oxidizing the substrate within the first and second trenches, and then filling the first and second trenches with insulative material.

24. The method of claim 23 wherein the protective material is removed prior to the lateral recessing of the nitride-containing layer.

25. The method of claim 23 wherein the protective material is removed after the lateral recessing of the nitride-containing layer.

26. The method of claim 23 wherein the lateral recessing of the nitride-containing layer is a second lateral recessing;

wherein the oxidizing of the substrate within the first and second trenches is a second oxidizing; and

further comprising;

after forming the first and second trenches and forming the protective material, first laterally recessing the nitride-containing layer;

after the first lateral recessing of the nitride-containing layer;

first oxidizing the substrate to form a first oxide layer extending within the first and second trenches;

forming the protective material to be within the first trenches and to be over the first oxide layer within the first trenches; and

while the protective material is within the first trenches, removing at least some of the first oxide layer from within the second trenches and then performing the extending of the second trenches to be deeper into the substrate.

27. The method of claim 26 wherein:

the nitride-containing layer of the masking stacks has exposed nitride-containing lateral surfaces during the first oxidizing of the substrate to form the first oxide layer extending within the first and second trenches; and

the first oxidation comprises dry thermal oxidation and does not appreciably oxidize the exposed nitride-containing lateral surfaces.

28. The method of claim 27 wherein:

the protective material within the first trenches extends to over the nitride-containing layer of the masking stacks of the memory array region and covers the nitride-containing lateral surfaces of the nitride-containing layer of the masking stacks of the memory array region; and

the protective material remains within the first trenches and over the nitride-containing lateral surfaces of the nitride-containing layer of the masking stacks of the memory array region during the second lateral recessing.

29. The method of claim 26 wherein:

the nitride-containing layer of the masking stacks has exposed nitride-containing lateral surfaces during the first oxidizing of the substrate to form the first oxide layer extending within the first and second trenches; and

the first oxidation comprises wet thermal oxidation and forms some of the oxide from the exposed nitride-containing lateral surfaces.

30. The method of claim 29 wherein the protective material within the first trenches is removed prior to the second lateral recessing.

31. The method of claim 29 wherein the protective material within the first trenches is removed after the second lateral recessing.

32. The method of claim 23 wherein the second trenches are spaced from one another by mesas of semiconductor material of the substrate having the masking stacks thereover;

wherein the oxidizing of the substrate within the second trenches forms rounded upper corners of the mesas; and

further comprising;

after the oxidizing, removing the masking stacks from over the mesas;

forming dielectric material over the mesas; and

forming electrically conductive material over the dielectric material.

33. The method of claim 32 wherein the dielectric material and electrically conductive material are together incorporated into a plurality of spaced lines.

34. The method of claim 32 wherein the mesas are second mesas;

wherein the first trenches are spaced from one another by first mesas of the semiconductor material having some of the masking stacks thereover;

wherein the masking stacks are removed from over the first mesas simultaneously with the removal of the masking stacks from over the second mesas; and

further comprising forming a plurality of wordlines extending across the first mesas.