Method of manufacturing a flash memory device
First Claim
1. A method of manufacturing a flash memory device, comprising:
- forming an insulation layer pattern on a substrate comprising a cell region and a peripheral region, the insulation layer pattern comprising openings selectively exposing portions of the substrate;
etching the exposed portions of the substrate to form trenches;
filling the trenches with an insulation material to form trench structures;
removing the insulation layer pattern to expose the surface of the substrate between the trench structures;
forming a tunnel oxide layer on the exposed surface of the substrate;
filling a gap space between the trench structures by forming a first conductive layer on the tunnel oxide layer;
partially removing the trench structures to form trench isolation structures and to form a conductive layer pattern from the first conductive layer;
forming a dielectric layer on the first conductive layer pattern and the trench isolation structures;
forming a doped second conductive layer on the dielectric layer to fill gap space between adjacent elements in the first conductive layer pattern;
removing the second conductive layer, the dielectric layer, the first conductive layer pattern and the tunnel oxide layer in the peripheral region to expose the surface of the substrate;
forming an insulation layer on the exposed surface of the substrate in the peripheral region;
forming a un-doped third conductive layer on the second conductive layer in the cell region, and on the insulation layer and the trench isolation structures in the peripheral region; and
forming a first gate structure in the cell region and a second gate structure in the peripheral region, wherein the first gate structure comprises the tunnel oxide layer, a floating gate electrode corresponding to the first conductive layer pattern, a dielectric layer pattern, and a control gate electrode comprising the second and third conductive layers, and the second gate structure comprising a gate insulation layer corresponding to the insulation layer and a gate conductive layer comprising the third conductive layer.
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Abstract
In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
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Citations
20 Claims
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1. A method of manufacturing a flash memory device, comprising:
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forming an insulation layer pattern on a substrate comprising a cell region and a peripheral region, the insulation layer pattern comprising openings selectively exposing portions of the substrate;
etching the exposed portions of the substrate to form trenches;
filling the trenches with an insulation material to form trench structures;
removing the insulation layer pattern to expose the surface of the substrate between the trench structures;
forming a tunnel oxide layer on the exposed surface of the substrate;
filling a gap space between the trench structures by forming a first conductive layer on the tunnel oxide layer;
partially removing the trench structures to form trench isolation structures and to form a conductive layer pattern from the first conductive layer;
forming a dielectric layer on the first conductive layer pattern and the trench isolation structures;
forming a doped second conductive layer on the dielectric layer to fill gap space between adjacent elements in the first conductive layer pattern;
removing the second conductive layer, the dielectric layer, the first conductive layer pattern and the tunnel oxide layer in the peripheral region to expose the surface of the substrate;
forming an insulation layer on the exposed surface of the substrate in the peripheral region;
forming a un-doped third conductive layer on the second conductive layer in the cell region, and on the insulation layer and the trench isolation structures in the peripheral region; and
forming a first gate structure in the cell region and a second gate structure in the peripheral region, wherein the first gate structure comprises the tunnel oxide layer, a floating gate electrode corresponding to the first conductive layer pattern, a dielectric layer pattern, and a control gate electrode comprising the second and third conductive layers, and the second gate structure comprising a gate insulation layer corresponding to the insulation layer and a gate conductive layer comprising the third conductive layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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17. A method of manufacturing a flash memory device, comprising:
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forming an insulation layer pattern on a substrate comprising a cell region and a peripheral region, the insulation layer pattern comprising openings selectively exposing portions of the substrate;
etching the exposed portions of the substrate to form trenches;
filling the trenches with an insulation material to form trench structures;
removing the insulation layer pattern to expose the surface of the substrate between the trench structures;
forming a tunnel oxide layer on the exposed surface of the substrate;
filling a gap space between the trench structures by forming a first conductive layer on the tunnel oxide layer;
partially removing the trench structures to form trench isolation structures and to form a conductive layer pattern from the first conductive layer;
forming a dielectric layer on the first conductive layer pattern and the trench isolation structures;
forming a doped second conductive layer on the dielectric layer to fill gap space between adjacent elements in the first conductive layer pattern;
removing the second conductive layer, the dielectric layer, the first conductive layer pattern and the tunnel oxide layer in the peripheral region to expose the surface of the substrate;
forming an insulation layer on the exposed surface of the substrate in the peripheral region;
forming a un-doped third conductive layer on the second conductive layer in the cell region, and on the insulation layer and the trench isolation structures in the peripheral region;
forming a first gate structure in the cell region and a second gate structure in the peripheral region, wherein the first gate structure comprises the tunnel oxide layer, a floating gate electrode corresponding to the first conductive layer pattern, a dielectric layer pattern, and a control gate electrode comprising the second and third conductive layers, and the second gate structure comprising a gate insulation layer corresponding to the insulation layer and a gate conductive layer comprising the third conductive layer;
doping the control gate and the gate conductive layer with impurities; and
,forming a silicon nitride capping insulation layer on the second conductive layer in the cell region. - View Dependent Claims (16, 18, 19, 20)
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Specification