Processing substrates using site-isolated processing

• US 20060292845A1
• Filed: 05/05/2006
• Published: 12/28/2006
• Est. Priority Date: 09/17/2004
• Status: Active Grant

• Current Assignee: Intermolecular Incorporated
• Original Assignee: Intermolecular Incorporated
• Inventors: Malhotra, Sandra G., Chiang, Tony P., Lazovsky, David E.
• Granted Patent: US 8,882,914 B2
• Time in Patent Office: Days
• US Class Current: 438/597
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/67028 for cleaning followed by drying, rinsing, stripping, blasting or the like
• CPC Class Codes: H01L 21/6708 using mainly spraying means, e.g. nozzles
• CPC Class Codes: H01L 21/67207 comprising a chamber adapted to a particular process
• CPC Class Codes: H01L 21/67745 characterized by movements or sequence of movements of transfer devices
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32

Abstract

Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.

Claims

1. A system comprising:

at least one interface configured to receive at least one substrate containing two or more regions;

a plurality of modules coupled to the at least one interface, at least one of the modules including a site-isolated reactor (SIR) configured for processing of the substrate that includes one or more of molecular self-assembly and combinatorial processing, wherein at least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate from at least one other region of the substrate; and

at least one handler configured to move the substrate between the interface and the plurality of modules.

2. The system of claim 1, wherein the plurality of modules includes at least one of a pre-processing module and a post-processing module.

3. The system of claim 2, wherein at least one module of the plurality of modules is configured to contain at least one of a plurality of different processes as appropriate to the processing and one or more processes contained in at least one other of the plurality of modules.

4. The system of claim 1, wherein the plurality of modules includes at least one of a wet processing module, a dry processing module, and a treatment module.

5. The system of claim 4, wherein the wet processing module includes at least one of clean modules, rinse modules, dry modules, electroless deposition modules, and electrochemical deposition modules.

6. The system of claim 4, wherein the dry processing module includes at least one of plasma processing modules, vapor phase processing modules, ion flux processing modules, radical flux processing modules, neutral flux processing modules, atomic flux processing modules, and chemical flux processing modules.

7. The system of claim 4, wherein the treatment module includes at least one of annealing modules, laser processing modules, vaporization modules, ultraviolet (UV) treatment modules, and e-beam treatment modules.

8. The system of claim 1, further comprising at least one controller coupled and configured to control an environment that includes at least one of an internal environment that is internal to at least one of the plurality of modules and an external environment that is external to at least one of the plurality of modules, wherein the controller controls at least one of temperature, pressure, and composition of the environment.

9. The system of claim 1, wherein the processing includes modifying the substrate, wherein the modifying includes at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications.

10. The system of claim 9, wherein the at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications include at least one of cleaning, surface modification, surface preparation, deposition, etching, planarization, chemical mechanical planarization, electrochemical mechanical planarization, lithography, patterning, implantation, irradiation, electromagnetic irradiation, microwave irradiation, radio frequency (RF) irradiation, thermal treatment, infrared (IR) treatment, ultraviolet (UV) treatment, deep ultraviolet (DUV) treatment, extreme ultraviolet (EUV) treatment, electron beam treatment, and x-ray treatment.

11. The system of claim 10, wherein deposition includes at least one of electrochemical deposition, electroless deposition, physical vapor deposition, chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, liquid phase epitaxy, chemical beam epitaxy, molecular beam epitaxy, molecular self-assembly, and evaporation.

12. The system of claim 10, wherein surface modification includes functionalization.

13. The system of claim 1, wherein the processing includes modifying at least one of the two or more regions of the substrate using at least one predefined sequence of modifications.

14. The system of claim 1, wherein the processing includes modifying at least one of the two or more regions using a predefined sequence of modifications and modifying the at least one other region using a different predefined sequence of modifications.

15. The system of claim 1, wherein the processing includes one or more of sequentially processing regions of at least one group of regions and simultaneously processing regions of at least one other group of regions.

16. The system of claim 1, wherein at least one module of the plurality of modules is configured to characterize the substrate.

17. The system of claim 16, wherein the characterizing includes one or more of sequentially characterizing regions of at least one group of regions and simultaneously characterizing regions of at least one other group of regions.

18. The system of claim 16, wherein the characterizing includes characterizing at least one region of the substrate for material properties that include at least one of optical properties, chemical composition, chemical reactivity, electrical properties, physical properties, magnetic properties, thermal properties, mechanical properties, and porosity.

19. The system of claim 16, wherein the characterizing includes characterizing at least one region of the substrate for structural properties that include at least one of material location, material distribution, material thickness, material step coverage, material continuity, and mechanical properties.

20. The system of claim 16, wherein the characterizing includes parametric testing of at least one region of the substrate that includes testing for at least one of yield, via chain yield, line yield, via resistance, line resistance, Kelvin resistance, leakage, and capacitance.

21. The system of claim 16, wherein the characterizing includes device testing of at least one region of the substrate, wherein device testing is selected from a group consisting of operational frequency, switching speed, power dissipation, mobility, transconductance, drive current, threshold voltage, capacitance, resistance, and charge density.

22. The system of claim 16, wherein the characterizing includes reliability testing of at least one region of the substrate that includes testing for at least one of stress migration, electromigration, bias thermal stress, thermal stress, mechanical stress, environmental stress of at least one environmental parameter, and time dependent dielectric breakdown.

23. The system of claim 1, wherein the SIR isolates the at least one region from the at least one other region during processing.

24. The system of claim 1, wherein the SIR includes at least one processing cell, wherein the processing cell and the substrate are configured to move relative to each other.

25. The system of claim 1, wherein each region of the substrate comprises a dielectric portion and an electrically conductive portion.

26. The system of claim 25, wherein processing includes forming a masking layer on the dielectric portion of at least one region of the substrate.

27. The system of claim 26, wherein forming the masking layer comprises selectively forming a molecularly self-assembled layer on the dielectric portion of at least one region of the substrate.

28. The system of claim 26, wherein forming the masking layer comprises forming masking layer material on the dielectric portion and the electrically conductive portion of at least one region and removing the masking layer material from the electrically conductive portion of the at least one region.

29. The system of claim 26, further comprising forming a capping layer on the electrically conductive portion of at least one region of the substrate.

30. The system of claim 29, wherein forming the capping layer comprises selectively forming capping layer material on the electrically conductive portion of at least one region of the substrate.

31. The system of claim 30, wherein the masking layer inhibits capping layer formation on the dielectric portion and generates a selective capping layer.

32. The system of claim 29, further comprising forming a dielectric barrier layer over the electrically conductive portion and the dielectric portion after forming the masking layer and the capping layer, wherein the dielectric barrier layer covers at least one of the capping layer and the masking layer.

33. The system of claim 29, further comprising removing the masking layer of at least one region of the substrate after forming the capping layer, wherein removing the masking layer generates a selective capping layer.

34. The system of claim 29, wherein forming the capping layer comprises forming capping layer material on the masking layer and the electrically conductive portion of at least one region of the substrate and removing capping layer material formed on the masking layer of the at least one region to generate a selective capping layer.

35. The system of claim 1, wherein the substrate is selected from a group including blanket wafers, patterned wafers, substrates including devices, substrates including functional chips, substrates including functional devices, and substrates including test structures.

36. The system of claim 1, wherein each region of the substrate includes at least one of semiconductors, integrated circuits, flat panel displays, optoelectronic devices, data storage devices, magnetoelectronic devices, magnetooptic devices, molecular electronic devices, solar cells, photonic devices, and packaged devices.

37. A system comprising:

at least one interface configured to receive at least one substrate;

at least one module coupled to the interface, the at least one module including at least one site-isolated reactor (SIR) configured for processing of the substrate that includes one or more of molecular self-assembly and combinatorial processing, wherein at least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate from at least one other region of the substrate; and

at least one handler coupled to the interface and configured to move the substrate between the interface and the at least one module.

38. A method comprising:

receiving a substrate that includes two or more regions;

processing a plurality of regions of the substrate, the processing including one or more of molecular self-assembly and combinatorial processing, wherein at least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate.

39. The method of claim 38, wherein the processing of the plurality of regions includes use of a site-isolated reactor (SIR) configured for the processing, wherein the SIR isolates at least one of the two or more regions from at least one other of the two or more regions during the processing.

40. The method of claim 39, wherein the SIR includes at least one processing cell, further comprising moving the processing cell and the substrate relative to each other.

41. The method of claim 38, wherein the processing of the plurality of regions includes use of a plurality of modules including at least one module configured for pre-processing operations and at least one module configured for post-processing operations.

42. The method of claim 41, wherein the plurality of modules includes at least one of a wet processing module, a dry processing module, and a treatment module.

43. The method of claim 38, further comprising controlling an environment of the processing, wherein the controlling includes control of at least one of temperature, pressure, and composition of the environment.

44. The method of claim 38, wherein the processing includes modifying the substrate, wherein the modifying includes at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications.

45. The method of claim 44, wherein the at least one of physical modifications, chemical modifications, electrical modifications, thermal modifications, magnetic modifications, photonic modifications, and photolytic modifications include at least one of cleaning, surface modification, surface preparation, deposition, etching, planarization, chemical mechanical planarization, electrochemical mechanical planarization, lithography, patterning, implantation, irradiation, electromagnetic irradiation, microwave irradiation, radio frequency (RF) irradiation, thermal treatment, infrared (IR) treatment, ultraviolet (UV) treatment, deep ultraviolet (DUV) treatment, extreme ultraviolet (EUV) treatment, electron beam treatment, and x-ray treatment.

46. The method of claim 45, wherein deposition includes at least one of electrochemical deposition, electroless deposition, physical vapor deposition, chemical vapor deposition, atomic layer deposition, vapor phase epitaxy, liquid phase epitaxy, chemical beam epitaxy, molecular beam epitaxy, molecular self-assembly, and evaporation.

47. The method of claim 45, wherein surface modification includes functionalization.

48. The method of claim 38, wherein the processing includes modifying at least one of the two or more regions of the substrate using at least one predefined sequence of modifications.

49. The method of claim 38, wherein the processing includes modifying at least one of the two or more regions using a predefined sequence of modifications and modifying the at least one other region using a different predefined sequence of modifications.

50. The method of claim 38, wherein the processing includes one or more of sequentially processing regions of at least one group of regions and simultaneously processing regions of at least one other group of regions.

51. The method of claim 38, further comprising characterizing at least one of the two or more regions of the substrate.

52. The method of claim 51, wherein the characterizing includes one or more of sequentially characterizing regions of at least one group of regions and simultaneously characterizing regions of at least one other group of regions.

53. The method of claim 38, wherein each region of the substrate comprises a dielectric portion and an electrically conductive portion.

54. The method of claim 53, wherein the processing includes forming a masking layer on the dielectric portion of at least one region of the substrate.

55. The method of claim 54, wherein forming the masking layer comprises selectively forming a molecularly self-assembled layer on the dielectric portion of at least one region of the substrate.

56. The method of claim 54, wherein forming the masking layer comprises forming masking layer material on the dielectric portion and the electrically conductive portion of at least one region and removing the masking layer material from the electrically conductive portion of the at least one region.

57. The method of claim 54, further comprising forming a capping layer on the electrically conductive portion of at least one region of the substrate.

58. The method of claim 57, wherein forming the capping layer comprises selectively forming capping layer material on the electrically conductive portion of at least one region of the substrate.

59. The method of claim 58, wherein the masking layer inhibits capping layer formation on the dielectric portion and generates a selective capping layer.

60. The method of claim 57, further comprising forming a dielectric barrier layer over the electrically conductive portion and the dielectric portion after forming the masking layer and the capping layer, wherein the dielectric barrier layer covers at least one of the capping layer and the masking layer.

61. The method of claim 57, further comprising removing the masking layer of at least one region of the substrate after forming the capping layer, wherein removing the masking layer generates a selective capping layer.

62. The method of claim 57, wherein forming the capping layer comprises forming capping layer material on the masking layer and the electrically conductive portion of at least one region of the substrate and removing capping layer material formed on the masking layer of the at least one region to generate a selective capping layer.

63. The method of claim 38, wherein the substrate is selected from a group including blanket wafers, patterned wafers, substrates including devices, substrates including functional chips, substrates including functional devices, and substrates including test structures.

64. The method of claim 38, wherein each region of the substrate includes at least one of semiconductors, integrated circuits, flat panel displays, optoelectronic devices, data storage devices, magnetoelectronic devices, magnetooptic devices, molecular electronic devices, solar cells, photonic devices, and packaged devices.