Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

• US 20060292866A1
• Filed: 06/23/2005
• Published: 12/28/2006
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Licensing, LLC (Teledyne Technologies Incorporated)
• Inventors: DeNatale, Jeffrey F., White, John, Stupar, Philip A., Warren, Les, Tsai, Chailun, Yao, Zhimin J., Garrett, Kathleen, Borwick, Robert L., Tench, Morgan
• Granted Patent: US 7,538,032 B2
• Time in Patent Office: Days
• US Class Current: 438/667
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases a gas that pushes the conductive material through the via to facilitate plating the via with the conductive material. In preferred embodiments, the fabrication of the substrate is conducted at low temperatures.

Claims

1. A process for fabricating a through-substrate via, the substrate having a first surface and a second surface, comprising:

forming a through-substrate via hole into the substrate;

forming an isolation material onto the substrate between the substrate and the conductive material, said isolation material being electrically insulating, continuous and substantially conformal; and

depositing conductive material into the via hole such that it is electrically continuous across its length.

2. A process as claimed in claim 1, further comprising:

preparing the isolation material for receiving the conductive material such that the conductive material reacts with the isolation material to plate the via; and

formation of the conductive material by means of a solution plating technique.

3. A process as claimed in claim 1, wherein forming the through-substrate via, forming isolation material, and depositing conductive material are performed at a low temperature range.

4. A process as claimed in claim 3, wherein said low temperature range is less than 100°

C.

5. A process as claimed in claim 3, wherein said low temperature is less than 400°

C.

6. A process as claimed in claim 1, wherein said isolation material is formed onto said substrate via deposition by vapor-deposition of organic materials, atomic layer deposition, plasma enhanced chemical vapor deposition, or polymer passivation coatings derived from substrate etch processing.

7. A process as claimed in claim 2, wherein the isolation material is parylene;

and the isolation material is prepared by activating it with a plasma.

8. A process as claimed in claim 2, wherein the isolation material is prepared by activating it with a seed layer which reacts with the conductive material.

9. A process as claimed in claim 8, wherein the seed layer is applied by:

absorbing tin onto the isolation material by bathing the substrate in a solution of stannous chloride and hydrochloric acid; and

bathing the substrate in a solution of palladium chloride and hydrochloric acid to deposit palladium on the substrate'"'"'s surface.

10. A process as claimed in claim 1, further comprising:

forming a plurality of vias into the substrate; and

plating said plurality of vias by the solution plating technique.

11. A process as claimed in claim 1, wherein the depth of the vias is greater than 100 μ

m.

12. A process as claimed in claim 1, wherein said through-substrate via is formed by:

etching a first cavity into the first surface of the substrate with a first diameter; and

etching a second cavity into the second surface of the substrate with a second diameter, wherein the first and second cavities form a single continuous aperture through the substrate.

13. A process as claimed in claim 12, wherein said first and second cavities extend to depths in the range of 20 μ

m-200 μ

m and 100 μ

m-350 μ

m, respectively.

14. A process as claimed in claim 13, wherein said first and second diameters are in the range of 2 μ

m-8 μ

m and 6 μ

m-25 μ

m, respectively,

15. A process as claimed in claim 1, wherein the conductive material is nickel.

16. A process as claimed in claim 1, wherein said flowing solution plating technique comprises an electroless deposition process.

17. A process as claimed in claim 12, wherein said first and second cavities are etched by a deep reactive ion etching process.

18. A process as claimed in claim 2, wherein the reaction to deposit the conductive material releases a gas that pushes the conductive material solution through the via to facilitate plating the via with the conductive material.

19. A process as claimed in claim 2, wherein a solution flow is generated by mechanical agitation to facilitate plating with the conductive material.

38. A process as claimed in claim 6, wherein said deposition by atomic layer deposition comprises deposition of inorganic oxides, said inorganic oxides being capable of providing electrical insulation and conformal surface coatings.

39. A process as claimed in claim 2, wherein the isolation material is prepared by activating it with a seed layer that reacts with the conductive material, said seed layer being deposited at low temperatures by atomic layer deposition or chemical vapor deposition.

40. A process as claimed in claim 8, wherein the seed layer is applied by:

bathing the substrate in a solution containing a metal acetate such that the vias are coated with the metal acetate;

heating the solution such that the metal acetate solution forms a thin metal layer on the interior surfaces of the vias.

20. A substrate having first and second surfaces, comprising:

a first plurality of substantially cylindrical cavities formed into the first surface to first depths and having first diameters;

a second plurality of substantially cylindrical cavities formed into the second surface to second depths greater than said first depths and having second diameters greater than or equal to said first diameters; and

said first and second plurality of cavities being coated with a conductive material and being mutually aligned to form a plurality of continuous conductive vias through said substrate.

21. A substrate as claimed in claim 20, further comprising circuitry residing nearer the first surface than the second surface, said first plurality of conductive vias form connections to said circuitry.

22. A substrate as claimed in claim 20, wherein said first plurality of conductive cavities is essentially solid and said second plurality of conductive cavities is essentially hollow.

23. A substrate as claimed in claim 20, wherein said first diameters and said second diameters are substantially equal.

24. A substrate as claimed in claim 20, wherein said first diameters are less than said second diameters.

25. A substrate as claimed in claim 20, the substrate being integrated with a plurality of substrates to form a multi-layer stack of wafers, the wafers being stacked and bonded together.

26. A multi-layered wafer stack as claimed in claim 25, wherein said bonding provides electrical interconnection between individual wafer layers.

27. A multi-layered wafer stack as claimed in claim 25, further comprising circuitry in at least one wafer, said first plurality of cavities form connections to said circuitry.

28. A substrate as claimed in claim 20, wherein at least one of said plurality of conductive cavities is partially solid.

29. A substrate as claimed in claim 20, wherein at least one of said second plurality of conductive cavities is partially solid.

30. A substrate as claimed in claim 25, further comprising circuitry, said circuitry residing on each of the plurality of wafers.

31. A substrate as claimed in claim 20, wherein said first and second diameters are in the range of 0.5 μ

m-300 μ

m.

32. A substrate as claimed in claim 25, wherein each wafer comprises a thickness of greater than 50 μ

m.

33. A substrate as claimed in claim 20, further comprising a thickness defined between said first surface and said second surface.

34. A substrate as claimed in claim 33, wherein said thickness is greater than 50 μ

m.

35. A substrate as claimed in claim 20, wherein said first and second depths extend to depths in the range of 10 μ

m-200 μ

m and 50 μ

m-1500 μ

m, respectively.

36. A substrate as claimed in claim 20, said first and second plurality of cavities being coated with an isolation material, said isolation material being prepared for receiving conductive material such that the conductive material reacts with the isolation material to plate the via.

37. A substrate as claimed in claim 20, said first and second plurality of cavities being coated with a metal acetate layer, said metal acetate layer being deposited by bathing the substrate in a solution containing metal acetate and thermally reacting the metal acetate solution to form the metal seed layer.

41. A process for plating a surface, comprising:

depositing a first material onto the surface;

preparing the first material for receiving a second material, the second material being electrically conductive, such that the second material reacts with the first material to plate the surface; and

depositing the second material onto the surface by means of a solution plating technique.

42. A process for plating a surface as claimed in claim 41, wherein the first material material is a polymer.

43. A process for plating a surface as claimed in claim 42, wherein the polymer is among the various types of parylene.

44. A process for plating a surface as claimed in claim 41, wherein preparing the first material comprises:

exposing the first material to a plasma to cause the surface to become hydrophilic.

45. A process for plating a surface as claimed in claim 41, wherein preparing the first material comprises:

applying a seed layer to the first material.

46. A process for plating a surface as claimed in claim 41, wherein the seed layer is applied by activation by metal precursor solutions, vapor deposited metal, or metal acetate decomposition.

47. A plated substrate having a surface, comprising:

a first layer of parylene deposited onto the surface of the substrate;

wherein the parylene surface is treated by exposing said parylene surface to a plasma;

a seed layer deposited onto the parylene layer, the seed layer deposited by bathing the substrate in a first solution containing first metal ions, the first solution releasing the first metal ions of the solution onto the parylene layer, and bathing the substrate in a second solution containing second metal ions, the second solution releasing the second metal ions onto the first metal ions in a monolayer; and

an electrodeposited conductive layer, wherein the conductive layer reacts with the thin layer of the second metal ion on the first metal ion to plate the substrate.