Generation sequences

• US 20060294312A1
• Filed: 05/27/2004
• Published: 12/28/2006
• Est. Priority Date: 05/27/2004
• Status: Abandoned Application

• Current Assignee: Silverbrook Research Pty Limited
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Walmsley, Simon Robert
• Application Number:
  US10/854,518
• Publication Number:
  US 20060294312A1
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 2221/2103 Challenge-response
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator
• CPC Class Codes: H04L 9/3215 using a plurality of channels network architectures or network communication protocols using different networks H04L63/18
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3271 using challenge-response

Abstract

A method for providing a sequence of nonces (R0, R1, R2, ) commencing with a current seed of a sequence of seeds (x1, x2, x3, . . . ), the method comprising: (a) applying a one-way function to the current seed, thereby to generate a current nonce; (b) outputting the current nonce; (c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and (c) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces.

Claims

1. A method for providing a sequence of nonces (R0, R1, R2, . . . ) commencing with a current seed of a sequence of seeds (x1, x2, x3, . . . ), the method comprising:

(a) applying a one-way function to the current seed, thereby to generate a current nonce;

(b) outputting the current nonce;

(c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and

(d) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces.

2. A method according to claim 1, wherein x1 is generated based on an initial seed x0, the initial seed having been generated by a random number generator.

3. A method according to claim 2, the initial seed x0 having been generated based on a stochastic process.

4. A method according to claim 3, wherein the next seed is generated from the current seed on the basis of a second function.

5. A method according to claim 4, wherein the second function is less cryptographically strong than the one way function.

6. A method according to claim 5, wherein the second function is additive.

7. A method according to claim 1, wherein the second function is a linear feedback shift register function.

8. A method according to claim 1, wherein the one way function is a hash function.

9. A method according to claim 1, wherein the hash function is SHA1.

31. A method according to claim 1, implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to:

(a) receive the digital signature from the second entity;

(b) receive the data; and

(c) authenticate the digital signature based on the received data and the first entity'"'"'s key.

32. A method according to claim 1, implemented in a first entity including:

a first bit-pattern

a non-volatile memory storing resource data,

a first base key for use with at least a first variant key;

a second variant key for use with a second base key, the second variant key being the result of a one way function applied to;

the second base key; and

the first bit-pattern or a modified bit-pattern based on the first bit-pattern.

33. A method according to claim 1, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to:

a base key; and

one or more of the at least one bit-patterns, respectively;

or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including

(a) determining that the predetermined event has happened; and

(b) enabling or disabling at least one of the first variant keys in response the predetermined event.

34. A method according to claim 1, implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein:

the first entity and the second entity share transport keys; and

the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.

35. A method according to claim 1, for storing a first bit-pattern in non-volatile memory of a device, the method comprising:

(a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result;

(b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and

(c) storing the second result in the memory, thereby indirectly storing the first bit-pattern.

36. A method according to claim 1, for storing a bit-pattern in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device:

(a) determining a first memory location; and

(b) storing the bit-pattern at the first memory location;

wherein the first memory locations are different in at least a plurality of the respective devices.

37. A method according to claim 1, for storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device:

(a) determining a first memory location; and

(b) storing a first of the at least one code segments in the memory at the first memory location;

wherein the first memory location is different in at least a plurality of the respective devices.

38. A method according to claim 1, for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored:

(a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result;

(b) applying a second function to the first result and the first bit-pattern, thereby to generate a-second result; and

(c) storing the second result in the memory, thereby indirectly storing the first bit-pattern;

wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.

10. A device for generating a sequence of nonces (R0, R1, R2, . . . ), the device including:

memory for storing a current seed of a sequence of seeds (x1, x2, x3, . . . )’

a processor configured to;

(a) apply a one way function to the current seed to generate a current nonce; and

(b) use the current seed to generate a next seed in the sequence of seeds, the seed so generated becoming the current seed; and

(c) storing the current seed in memory.

11. A device according to claim 10, configured to generate x1 in the seed sequence based on an initial seed x0, the initial seed being stored in a non-volatile manner in the device.

12. A device according to claim 10, wherein x0 was generated by a random number generator.

13. A device according to claim 12, the initial seed x0 having been generated based on a stochastic process.

14. A device according to claim 10, wherein the processor is configured to generate the next seed by applying a second function to the current seed.

15. A device according to claim 14, wherein the second function is less cryptographically strong than the one way function.

16. A device according to claim 15, wherein the second function is additive.

17. A device according to claim 10, wherein the second function is a linear feedback shift register function.

18. A device according to claim 10, wherein the memory is non-volatile.

19. A device according to claim 17, wherein the memory is flash memory.

20. A device according to claim 10, wherein the device comprises one or more integrated circuits.

21. A device according to claim 10, wherein the device comprises a monolithic integrated circuit.

22. A device according to claim 10, wherein the one way function is a hash function.

23. A device according to claim 22, wherein the hash function is SHA1.

24. A method of manufacturing a series of devices, each of the devices being in accordance with claim 10 and including a non-volatile memory, the method comprising:

generating a bit-pattern on the basis of a random or pseudo random process;

storing the bit-pattern in a non-volatile manner in the device;

wherein the device is configured to use the bit-pattern as an initial current seed, and to store subsequent generated seeds in the non-volatile memory.

25. A method according to claim 24, wherein the step of storing the bit-pattern in a non-volatile manner includes storing the value in a place other than in the non-volatile memory.

26. A method according to claim 25, wherein the bit-pattern is stored in non-erasable form.

27. A method according to claim 24, including the step of storing a program on the device, the program including the one way function for generating the current nonce from the current seed.

28. A method according to claim 27, wherein the one way function is a hash function.

29. A method according to claim 27, wherein the one way function is non-compressing.

30. A method according to claim 28, wherein the hash function is SHA1