Bios security management

• US 20060294349A1
• Filed: 06/22/2005
• Published: 12/28/2006
• Est. Priority Date: 06/22/2005
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Spottswood, Jason
• Granted Patent: US 7,350,067 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]

Abstract

In one embodiment a computer system, comprises a processor, a basic input/output system (BIOS) including logic instructions which, when executed by the processor, configure the processor to initiate power on self test (POST) processing in the basic input/output system (BIOS) of a computing device, detect a connection to a remote memory device, and write an access level indicator stored on the remote memory device to an output device.

Claims

1. A method, comprising:

initiating power on self test (POST) processing in the basic input/output system (BIOS) of a computing device;

detecting a connection to a remote memory device;

writing an access level indicator stored on the remote memory device to an output device.

2. The method of claim 1, wherein detecting a connection to a remote memory device comprises:

detecting an interrupt signal generated in response to the remote memory device; and

initiating a handshake protocol to establish communication with the remote memory device.

3. The method of claim 2, further comprising reading the access level indicator stored on the remote memory device.

4. The method of claim 1, wherein detecting a connection to a remote memory device comprises poll system hardware to determine whether a memory device is connected to the computing device.

5. The method of claim 1, wherein reading an access level comprises decoding the access level indicator.

6. The method of claim 1, further comprising:

receiving a verification signal from a user associated with the remote memory device; and

granting an access level to a user based on at least one of the access level indicator or the verification signal.

7. The method of claim 1, wherein writing the access level indicator stored on the remote memory device to an output device comprises presenting the access level indicator on a display screen.

8. A computer system, comprising:

a processor;

a basic input/output system (BIOS) including logic instructions which, when executed by the processor, configure the processor to;

initiate power on self test (POST) processing in the basic input/output system (BIOS) of a computing device;

detect a connection to a remote memory device; and

write an access level indicator stored on the remote memory device to an output device.

9. The computer system of claim 8, wherein the BIOS further comprises logic instructions which, when executed by the processor, configure the processor to:

detect an interrupt signal generated in response to the remote memory device; and

initiate a handshake protocol to establish communication with the remote memory device.

10. The computer system of claim 8, wherein the BIOS further comprises logic instructions which, when executed by the processor, configure the processor to read an access level indicator stored on the remote memory device.

11. The computer system of claim 8, wherein the BIOS further comprises logic instructions which, when executed by the processor, configure the processor to poll system hardware to determine whether a memory device is connected to the computing device.

12. The computer system of claim 8, wherein the BIOS further comprises logic instructions which, when executed by the processor, configure the processor to decode the access level indicator.

13. The computer system of claim 8, wherein the BIOS further comprises logic instructions which, when executed by the processor, configure the processor to:

receive a verification signal from a user associated with the remote memory device; and

grant an access level to a user based on at least one of the access level indicator or the verification signal.

14. The computer system of claim 8, wherein the BIOS further comprises logic instructions which, when executed by the processor, configure the processor to present the access level indicator on a display screen.

15. A computer program product comprising logic instructions stored on a computer-readable medium which, when executed by a computer processor, configure the processor to:

initiate power on self test (POST) processing in the basic input/output system (BIOS) of a computing device;

detect a connection to a remote memory device;

write an access level indicator stored on the remote memory device to an output device.

16. The computer program product of claim 15, further comprising logic instructions which, when executed by the processor, configure the processor to:

detect an interrupt signal generated in response to the remote memory device; and

initiate a handshake protocol to establish communication with the remote memory device.

17. The computer program product of claim 15, further comprising logic instructions which, when executed by the processor, configure the processor to read an access level indicator stored on the remote memory device.

18. The computer program product of claim 15, further comprising logic instructions which, when executed by the processor, configure the processor to decode the access level indicator.

19. The computer program product of claim 15, further comprising logic instructions which, when executed by the processor, configure the processor to:

receive a verification signal from a user associated with the remote memory device; and

grant an access level to a user based on at least one of the access level indicator or the verification signal.

20. The computer program product of claim 15, further comprising logic instructions which, when executed by the processor, configure the processor to present the access level indicator on a display screen.

21. A computer system, comprising:

a processor;

a basic input/output system (BIOS) module;

means for initiating power on self test (POST) processing in the computing device;

means for detecting a connection to a remote memory device; and

means for writing an access level indicator stored on the remote memory device to an output device.

22. The computer system of claim 21, further comprising:

means for detecting an interrupt signal generated in response to the remote memory device; and

means for initiating a handshake protocol to establish communication with the remote memory device.

23. The computer system of claim 21, further comprising:

means for reading access level indicator stored on the remote memory device;

means for receiving a verification signal from a user associated with the remote memory device; and

means for granting an access level to a user based on at least one of the access level indicator or the verification signal.