System and method of using a protected non-volatile memory

• US 20060294397A1
• Filed: 06/24/2005
• Published: 12/28/2006
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Baker, David Cureton
• Granted Patent: US 8,639,946 B2
• Time in Patent Office: Days
• US Class Current: 713/193
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

The disclosure includes a system and method of using a processor and protected memory. In a particular embodiment, the system includes a processor, a volatile memory accessible to the processor, and a first nonvolatile memory accessible to the processor. The first nonvolatile memory includes a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit. The system includes a second nonvolatile memory including data to be transferred to the volatile memory.

Claims

1. A system comprising:

a processor;

a volatile memory accessible to the processor;

a first nonvolatile memory accessible to the processor, the first nonvolatile memory including a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit; and

a second nonvolatile memory, the second nonvolatile memory including data to be transferred to the volatile memory.

2. The system of claim 1, wherein a key set is stored within the first portion, the key set to perform at least one of authentication and decryption of the data in the second nonvolatile memory upon transfer to the volatile memory.

3. The system of claim 1, wherein the data to be transferred is program code.

4. The system of claim 3, wherein the program code includes a plurality of authentication words.

5. The system of claim 3, wherein the shield bit is set after performing an operation to transfer the program code from the second nonvolatile memory to the volatile memory but before execution by the processor of the program code.

6. The system of claim 5, wherein the shield bit is set prior to execution of a first instruction of the program code.

7. The system of claim 1, further comprising external test interface protection logic, the external test interface protection logic responsive to an external test clock input, and wherein the shield bit is set after detection of a number of cycles of the external test clock input exceeds a threshold.

8. The system of claim 7 wherein the threshold is less than 40 clock cycles.

9. The system of claim 8, wherein the threshold is 20 clock cycles and wherein the external test clock input is a JTAG clock associated with a JTAG instruction.

10. The system of claim 2, wherein the key set is associated with a unique product manufacturer.

11. The system of claim 1, wherein the second portion of the first nonvolatile memory includes audio data.

12. The system of claim 2, wherein the key set includes an authentication key and a decryption key.

13. The system of claim 1, wherein the first nonvolatile memory is read only memory and the second nonvolatile memory is flash memory.

14. A memory device comprising:

a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation; and

a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit.

15. The memory device of claim 14, further comprising a read multiplexer coupled to the first portion of memory, the multiplexer controlled at least in part in response to the shield bit.

16. The memory device of claim 15, wherein the multiplexer outputs a value from the first portion of memory during the unshielded mode of operation and wherein the multiplexer outputs a fixed output value indicating an error condition during the shielded mode of operation.

17. The memory device of claim 14, wherein the shield bit is stored in a write once memory device so that the shield bit is not user modifiable after a single write operation.

18. A method of activating a processor device having access to a read only memory, the method comprising:

powering up the processor device, wherein the read only memory has a protected portion of memory that is shieldable but that is in an unshielded mode upon powerup;

reading a key set from the protected portion of memory in connection with performing a data transfer to a random access memory (RAM); and

after performing the data transfer, setting the protected portion of the memory to a shielded mode where the key set is no longer readable from the read only memory.

19. The method of claim 18, wherein after reading the key set, the key set is used to perform authentication and decryption with respect to the data transferred to the RAM.

20. The method of claim 18, wherein the data transferred to the RAM includes program instructions and further comprising executing the program instructions by the processor device.

21. The method of claim 18, wherein the protected portion further includes key set extraction data that is readable when the protected portion is in the unshielded mode.

22. The method of claim 18, wherein a shield bit associated with the protected portion of the memory is stored in a write once memory.