Block contact architectures for nanoscale channel transistors

• US 20070001219A1
• Filed: 06/30/2005
• Published: 01/04/2007
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Radosavljevic, Marko, Kavalieros, Jack, Majumdar, Amlan, Datta, Suman, Chau, Robert, Doyle, Brian, Doczy, Mark, Brask, Justin
• Granted Patent: US 7,279,375 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Claims

1. A device comprising:

a plurality of parallel semiconductor bodies, each of said plurality of parallel bodies having a top surface and a pair of laterally opposite sidewalls, each of said parallel bodies having a channel portion between a source region and a drain region;

a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;

a metal source contact coupled to and extending between said source regions of each of said plurality of parallel bodies; and

a metal drain contact coupled to and extending between said drain regions of each of said plurality of parallel bodies.

2. The device of claim 1 wherein said parallel bodies have a first width and a first pitch, wherein said first pitch is less than a pitch which can be defined by a photolithography process.

3. The device of claim 2 wherein said photolithography process uses 193 nanometer lithography.

4. The device of claim 2 wherein said first pitch is less than 110 nanometers.

5. The device of claim 2 wherein said pitch is one half of said pitch which can be defined by said photolithography process.

6. The device of claim 1 further comprising a source landing pad in direct contact with said source regions of said plurality of parallel bodies, wherein said source landing pad is formed from the same material as said parallel bodies and wherein said metal source contact is formed in direct contact with said source landing pad.

7. The device of claim 1 further comprising a drain landing pad in direct contact with said drain regions of said plurality of parallel bodies, wherein said drain landing pad is formed from the same material as said plurality of parallel bodies and wherein said metal drain contact is formed in direct contact with said drain landing pad.

8. The device of claim 1 wherein said plurality of parallel bodies formed from a material selected from the group consisting of silicon, germanium, silicon germanium, GaAs, InSb and carbon nanotubes.

9. The semiconductor device of claim 8 wherein said plurality of parallel bodies are formed on an insulating substrate.

10. A device comprising:

a plurality of parallel semiconductor bodies, each of said plurality of parallel bodies having a top surface and a pair of laterally opposite sidewalls, each of said parallel bodies having a channel portion between a source region and a drain region;

a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;

a first metal contact and a second metal contact, wherein at least one of said first metal contact and said second metal contact is coupled to and extending between said plurality of parallel bodies.

11. A method of forming a semiconductor device comprising:

forming a plurality of parallel spacers having a first pitch above a semiconductor film;

etching said semiconductor film in alignment with said plurality of parallel spacers to form a plurality of parallel semiconductor bodies;

forming a single gate electrode over and adjacent to said plurality of parallel semiconductor bodies;

forming a source region and a drain region in each of said parallel semiconductor bodies on opposite sides of said gate electrode;

forming a single metal source contact coupled to and extending between said source regions of said semiconductor bodies; and

forming a single metal drain contact coupled to and extending between said drain regions of said plurality of semiconductor bodies.

12. The method of claim 4011 wherein said plurality of parallel spacers is formed by a method comprising:

forming a first pattern of parallel features having a second pitch from a first material, wherein said second pitch is greater than said first pitch;

blanket depositing a comformal film of a second material over and adjacent to said first pattern of parallel features; and

anisotropically etching said conformal film to form said plurality of parallel spacers from said second material; and

removing said first pattern of parallel features of said first material.

13. The method of claim 12 wherein said first pattern of parallel features are formed by forming a photoresist mask over said first material, and anisotropically etching said first material in alignment with said photoresist mask.

14. The method of claim 13 wherein said photoresist mask is formed by blanket depositing a photoresist film and patterning said photoresist film into a plurality of parallel features having said second pitch which is the smallest pitch which can be defined in said photoresist film utilizing a photolithography process.

15. A method of forming a semiconductor device comprising:

forming a plurality of parallel semiconductor bodies, wherein each of said semiconductor bodies has a channel region between a source region and a drain region;

forming a single gate electrode over and adjacent to said channel regions of said plurality of parallel semiconductor bodies;

forming a dielectric layer over said gate electrode and said plurality of parallel semiconductor bodies;

forming a single drain opening in said dielectric layer which extends between and exposes said drain regions of said plurality of parallel semiconductor bodies and forming a single source opening in said dielectric layer which extends between and exposes said source regions of said semiconductor bodies; and

filling said single drain opening and said single source opening with a metal film wherein said metal film is in contact with said source regions and said drain regions of said plurality of parallel semiconductor bodies.

16. The method of claim 15 further comprise wherein said metal film is blanket deposited into said source opening and said drain opening and onto the top surface of said dielectric layer;

and

polishing back said metal film from the top surface of said dielectric layer to form a single drain contact and a single source contact.

17. The method of claim 16 wherein said metal film is formed in said opening utilizing an electroless or electrolytic deposition process.