Superjunction semiconductor device

• US 20070001230A1
• Filed: 06/29/2005
• Published: 01/04/2007
• Est. Priority Date: 06/29/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Lee, Jae-gil, Jang, Ho-cheol, Jung, Jin-young
• Granted Patent: US 8,084,815 B2
• Time in Patent Office: Days
• US Class Current: 257/367
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.

Claims

1. A superjunction semiconductor device comprising:

an edge p pillar having a rectangular ring shape with rounded corners;

an active region surrounded by the edge p pillar, the active region having active p pillars having a vertical stripe shape arranged in an active n region, the top and bottom ends of the active p pillars being separated from the edge p pillar; and

a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.

2. The superjunction semiconductor device of claim 1, wherein the distance between the central axis of the edge p pillar and the top end of each active p pillar is equal to half the distance between the vertical central axes of neighboring active p pillars.

3. The superjunction semiconductor device of claim 2, wherein the distance between the central axis of each side of the edge p pillar and the vertical central axis of the corresponding active p pillar disposed closest to each side of the edge p pillar is identical to the distance between the vertical central axes of neighboring active p pillars.

4. The superjunction semiconductor device of claim 1, wherein the width of the edge p pillar is identical to the width of each of the active p pillars.

5. The superjunction semiconductor device of claim 1, wherein the widths of the upper and lower parts of the active p pillars are gradually decreased or increased toward each end of the upper and lower parts in the corners of the active region.

6. The superjunction semiconductor device of claim 5, wherein the widths of the upper and lower parts of the active p pillars are gradually decreased when the quantity of p charges is larger than the quantity of n charges and gradually increased when the quantity of p charges is smaller than the quantity of n charges.

7. The superjunction semiconductor device of claim 1, further comprising subsidiary p pillars arranged in the active n region to compensate for the small quantity of p charges in the active p pillars in the corners of the active region.

8. The superjunction semiconductor device of claim 7, wherein the subsidiary p pillars have bar shapes vertically arranged in the active n region in the corners of the active region.

9. The superjunction semiconductor device of claim 7, wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n region in the corner of the active region.

10. The superjunction semiconductor device of claim 7, wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n region in the corners of the active region.

11. A superjunction semiconductor device comprising:

an edge p pillar having a first width and a rectangular ring shape with rounded corners;

an active region surrounded by the edge p pillar, the active region having active p pillars having vertical stripe shapes with a second width twice the first width and active n pillars, the active p pillars and the active n pillars being alternately arranged horizontally in the active region; and

a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.

12. The superjunction semiconductor device of claim 11, wherein the distance between the central axis of each side of the edge p pillar and the vertical central axis of the corresponding active p pillar disposed closest to each side of the edge p pillar is equal to half the distance between the vertical central axes of neighboring active p pillars.

13. The superjunction semiconductor device of claim 11, wherein the widths of the upper and lower parts of the active p pillars are gradually decreased or increased toward each end of the upper and lower parts in the corners of the active region.

14. The superjunction semiconductor device of claim 13, wherein the widths of the upper and lower parts of the active p pillars are gradually decreased when the quantity of p charges is larger than the quantity of n charges and gradually increased when the quantity of p charges is smaller than the quantity of n charges.

15. The superjunction semiconductor device of claim 11, further comprising subsidiary p pillars arranged in the active n pillars to compensate for the small quantity of p charges in the active p pillars in the corners of the active region.

16. The superjunction semiconductor device of claim 15, wherein the subsidiary p pillars have bar shapes vertically arranged in the active n pillars in the corners of the active region.

17. The superjunction semiconductor device of claim 15, wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n pillars in the corners of the active region.

18. The superjunction semiconductor device of claim 15, wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n pillars in the corners of the active region.

19. A superjunction semiconductor device comprising:

an active region having active p pillars and active n pillars having vertical stripe shapes, the active p pillars and the active n pillars being alternately arranged horizontally in the active region;

an edge p pillar having a rectangular ring shape with rounded corners, the edge p pillar including an outer region surrounding the active region and an inner region disposed on the sides of the active region; and

a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.

20. The superjunction semiconductor device of claim 19, wherein the width of the corners, and upper and lower parts of the edge p pillar where only the outer region is arranged is equal to half the width of each of the active p pillars.

21. The superjunction semiconductor device of claim 20, wherein the width of the edge p pillar where both the outer region and the inner region are arranged is identical to the width of each of the active p pillars.

22. The superjunction semiconductor device of claim 19, wherein the distance between the boundary between the outer region and the inner region and the vertical central axis of the active p pillar disposed closest to the edge p pillar is identical to the distance between the vertical central axes of neighboring active p pillars.

23. The superjunction semiconductor device of claim 19, wherein the widths of the upper and lower parts of the active p pillars are gradually decreased or increased toward each end of the upper and lower parts in the corners of the active region.

24. The superjunction semiconductor device of claim 23, wherein the widths of the upper and lower parts of the active p pillars are gradually decreased when the quantity of p charges is larger than the quantity of n charges and gradually increased when the quantity of p charges is smaller than the quantity of n charges.

25. The superjunction semiconductor device of claim 19, further comprising subsidiary p pillars arranged in the active n pillars to compensate for the small quantity of p charges in the active p pillars in the corners of the active region.

26. The superjunction semiconductor device of claim 25, wherein the subsidiary p pillars have bar shapes vertically arranged in the active n pillars in the corners of the active region.

27. The superjunction semiconductor device of claim 25, wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n pillars in the corners of the active region.

28. The superjunction semiconductor device of claim 25, wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n pillars in the corners of the active region.

29. A superjunction semiconductor device comprising:

an active region including active p pillars and active n pillars having vertical stripe shapes alternately arranged horizontally in the active region; and

island p regions arranged in a matrix form at predetermined intervals in the corners of the active region, the island p regions being arranged in n regions having the same impurity concentration as that of the active n pillars; and

an edge p pillar having a rectangular ring shape with rounded corners surrounding the active region.

30. The superjunction semiconductor device of claim 29, further comprising a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.

31. A superjunction semiconductor device comprising:

an active region including active p pillars and active n pillars having vertical stripe shapes alternately arranged horizontally in the active region; and

subsidiary p pillars arranged in the active n pillars in corners of the active region, the subsidiary p pillars compensating for an imbalance between the quantity of p charges and the quantity of n charges; and

an edge p pillar having a rectangular ring shape with rounded corners surrounding the active region.

32. The superjunction semiconductor device of claim 31, wherein the subsidiary p pillars have bar shapes vertically arranged in the active n pillars in the corners of the active region.

33. The superjunction semiconductor device of claim 31, wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the active n pillars in the corners of the active region.

34. The superjunction semiconductor device of claim 31, wherein the subsidiary p pillars have bent belt shapes arranged along the inner side of and contacting the edge p pillar in the active n pillars in the corners.