Distributed networks of electric double layer capacitor supervisory controllers and networks thereof

• US 20070001651A1
• Filed: 07/02/2005
• Published: 01/04/2007
• Est. Priority Date: 07/02/2004
• Status: Abandoned Application

• Current Assignee: Troy Harvey
• Original Assignee: Troy Harvey
• Inventors: Harvey, Troy
• Application Number:
  US11/173,481
• Publication Number:
  US 20070001651A1
• Time in Patent Office: Days
• US Class Current: 320/166
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices

Abstract

Disclosed is an electric double layer capacitor, having a multiplicity of cells occupying a single package, wherein the individual cells are managed and balanced by networkable embedded circuitry also contained within the same package.

Claims

1. An electric double layer capacitor module comprising:

an array of the least two electric double layer capacitor cells;

an embedded cell balancing circuit; and

a means of networking the embedded cell balancing circuit to another such circuit of another such module or charge controller;

wherein said capacitors, balancing circuits, and means of networking are all housed in a single enclosure;

2. The enclosure of claim 1, wherein the enclosure may comprise a barrier layer forming an air-tight seal, such that the capacitor and circuitry is contained within the air-tight seal.

3. The enclosure of claim 2, wherein the enclosure comprises a container, foil, laminate, or coating selected from the group consisting of a metal, ceramic, or polymer laminate forming a substantially hermetic barrier

4. The electric double layer capacitor module of claim 1, wherein the terminal ends of the electric double layer capacitor array are electrically connected to two power terminals as provided by electrical feed-throughs projecting through the enclosure envelope or electrically conducting terminal surfaces integral to the module enclosure.

5. The electric double layer capacitor module of claim 1, wherein the means of networking comprises one or more terminals connected internally to the embedded cell balancing circuitry and electrically connected to terminals as provided by electrical feed-throughs projecting through the enclosure envelope or electrically conducting terminal surfaces integral to the module enclosure.

6. The charge balancing circuitry of claim 1, wherein the circuitry has a switched bypass device connected in parallel across each of the double layer capacitors in the modules capacitor array.

7. The switched bypass device of claim 6, wherein the device may selected from the group consisting of transistors, MOSFETS, FETS, IGBTS, photo-coupled diodes, photo-coupled transistors, and relays.

8. The switched bypass device of claim 6, wherein the device may further comprise a resistor and/or diode.

9. The switched bypass device of claim 6, wherein the switch is pulse modulated.

10. The switched bypass device of claim 6, wherein the bypass switching is engaged while the electric double layer capacitor of the module having the highest voltage is above a minimum voltage threshold.

11. The charge balancing circuitry of claim 1, wherein the circuitry has at least one switched intermediary energy storage element, which can be switched into electrical parallel with any of the double layer capacitors in the module array via a switch matrix, whereby allowing charge shuttling between said double layer capacitors via the intermediary storage capacitor.

12. The intermediary energy storage element of claim 11, wherein the element may be comprised from at least one of the group:

capacitors, inductors, and transformers.

13. The charge shuttling of claim 11, wherein the charge shuttling between capacitors in the array is engaged only while a capacitor of the module is above a minimum voltage threshold.

14. The voltage threshold of claim 13, wherein the threshold voltage comprises a hysteresis function, such that the charge shuttling between capacitors in the array is engaged only while a capacitor of the module is above minimum voltage threshold during charge, but disengages at a higher voltage threshold during discharge.

15. The embedded cell balancing circuitry of claim 11, wherein the each of the cells in the array of electric double layer capacitors are compared in pairs, one to another, by a voltage comparison circuit such that if difference between any pair exceeds a threshold voltage, the higher of the two electric double layer capacitors is connected in parallel with an intermediary energy storage element, charging said storage element, then disconnected, and then connected in parallel with the electric double layer capacitor of lower charge.

16. The embedded cell balancing circuitry of claim 15, wherein the charge shuttling sequence is repeated an adaptive number of times between the same two electric double layer capacitors before continuing on to test other pairs of double layer capacitors in the array.

18. The embedded cell balancing circuitry of claim 15, wherein the voltage comparison circuitry compares each adjacent pair of capacitors in the array, in circular fashion such that at the end of the array the last capacitor is compared to the first capacitor at the beginning.

19. A network of the double layer capacitor modules described in claim 1, networked together where a signal or message from any one of said capacitor modules indicates to an external charge controller to stop charging the plurality of electric double layer capacitor modules in the network.

20. A method of networking a parallel array of at least one double layer capacitor modules as described in claim 1, wherein each capacitor module has two power terminals, and a network terminal;

wherein the modules in the array are connected together in electrical parallel with a charge controller, and the network terminals of each module are connected to each other and also to the charge controller, such that the charge controller charges the array of modules until one module signals that a electric double layer capacitor within the module enclosure has reached top-of-charge at which point the controller stops charging the array.

17. The embedded cell balancing circuitry of 11, wherein after the circuitry determines the highest and lowest voltage electric double layer capacitor cells in the series array, and if the difference in voltage between those cells is greater than a threshold voltage, the circuit shuttles charge between the two.